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1. 发明申请

US20090031082A1 Accessing a Cache in a Data Processing Apparatus 审中-公开
标题翻译：访问数据处理设备中的缓存
公开(公告)号：US20090031082A1
公开(公告)日：2009-01-29
申请号：US12224725
申请日：2006-03-06
申请人： Simon Andrew Ford , Mrinmoy Ghosh , Emre Ozer , Stuart David Biles
发明人： Simon Andrew Ford , Mrinmoy Ghosh , Emre Ozer , Stuart David Biles
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0864 , G06F2212/1016 , G06F2212/6032 , Y02D10/13
摘要： A data processing apparatus is provided having processing logic for performing a sequence of operations, and a cache having a plurality of segments for storing data values for access by the processing logic. The processing logic is arranged, when access to a data value is required, to issue an access request specifying an address in memory associated with that data value, and the cache is responsive to the address to perform a lookup procedure during which it is determined whether the data value is stored in the cache. Indication logic is provided which, in response to an address portion of the address, provides for each of at least a subject of the segments an indication as to whether the data value is stored in that segment. The indication logic has guardian storage for storing guarding data, and hash logic for performing a hash operation on the address portion in order to reference the guarding data to determine each indication. Each indication indicates whether the data value is either definitely not stored in the associated segment or is potentially stored with the associated segment, and the cache is then operable to use the indications produced by the indication logic to affect the lookup procedure performed in respect of any segment whose associated indication indicates that the data value is definitely not stored in that segment. This technique has been found to provide a particularly power efficient mechanism for accessing the cache.
摘要翻译：提供了具有用于执行操作序列的处理逻辑的数据处理装置，以及具有多个段的高速缓存，用于存储由处理逻辑进行访问的数据值。当需要访问数据值时，处理逻辑被布置为发出指定与该数据值相关联的存储器中的地址的访问请求，并且高速缓存响应于地址以执行查找过程，在该过程中确定是否数据值存储在缓存中。提供指示逻辑，响应于地址的地址部分，为段中的至少一个对象提供关于数据值是否存储在该段中的指示。指示逻辑具有用于存储保护数据的保护存储和用于对地址部分执行散列操作的散列逻辑，以引用保护数据来确定每个指示。每个指示指示数据值是否绝对不存储在相关联的段中或潜在地与相关联的段相关联，并且高速缓存然后可操作地使用由指示逻辑产生的指示来影响关于任何其相关联的指示表明数据值绝对不存储在该段中。已经发现这种技术提供了用于访问高速缓存的特别有效的机构。

2. 发明申请

US20080209133A1 Managing cache coherency in a data processing apparatus 有权
公开(公告)号：US20080209133A1
公开(公告)日：2008-08-28
申请号：US11709279
申请日：2007-02-22
申请人： Emre Ozer , Stuart David Biles , Simon Andrew Ford
发明人： Emre Ozer , Stuart David Biles , Simon Andrew Ford
IPC分类号： G06F13/00
CPC分类号： G06F12/0831 , G06F12/0822 , Y02D10/13
摘要： A data processing apparatus and method are provided for managing cache coherency. The data processing apparatus comprises a plurality of processing units, each having a cache associated therewith, and each cache having indication circuitry containing segment filtering data. The indication circuitry is responsive to an address portion of an address specified by an access request from an associated processing unit to reference the segment filtering data in order to provide, for each of at least a subset of the segments of the associated cache, an indication as to whether the data is either definitely not stored in that segment or is potentially stored in that segment. Further, in accordance with the present invention, cache coherency circuitry is provided which employs a cache coherency protocol to ensure data accessed by each processing unit is up-to-date. The cache coherency circuitry has snoop indication circuitry associated therewith whose content is derived from the segment filtering data of each indication circuitry. For certain access requests, the cache coherency circuitry initiates a coherency operation during which the snoop indication circuitry is referenced to determine whether any of the caches require subjecting to a snoop operation. For each cache for which it is determined a snoop operation should be performed, the cache coherency circuitry is arranged to issue a notification to that cache identifying the snoop operation to be performed. By taking advantage of information already provided in association with each cache in order to form the content of the snoop indication circuitry, significant hardware cost savings are achieved when compared with prior art techniques. Further, through use of such an approach, it is possible in embodiments of the present invention to identify the snoop operation not only on a cache-by-cache basis, but also for a particular cache to identify which segments of that cache should be subjected to the snoop operation.

3. 发明授权

US08621336B2 Error correction in a set associative storage device 有权
公开(公告)号：US08621336B2
公开(公告)日：2013-12-31
申请号：US12222085
申请日：2008-08-01
申请人： Simon John Craske , Andrew Christopher Rose , Paul Stanley Hughes , Antony John Penton , Richard York , Simon Andrew Ford , Stuart David Biles , Alex James Waugh
发明人： Simon John Craske , Andrew Christopher Rose , Paul Stanley Hughes , Antony John Penton , Richard York , Simon Andrew Ford , Stuart David Biles , Alex James Waugh
IPC分类号： G06F11/00
CPC分类号： G06F11/1064
摘要： A data processing apparatus is provided comprising processing circuitry for performing data processing operations, a set associative storage device for storing data values for access by the processing circuitry when performing data processing operations, error detection circuitry for performing, for each access to the storage device, an error detection operation on the data value accessed, and maintenance circuitry associated with the storage device for performing one or more maintenance operations. The processing circuitry is arranged to issue an error detection maintenance request to the maintenance circuitry specifying at least one specific physical location within the storage device, and the maintenance circuitry is responsive to the error detection maintenance request to perform at least one dummy access to the at least one specific physical location within the storage device and to provide the processing circuitry with error status information derived from the error detection operation performed by the error detection circuitry in respect of said at least one dummy access.

4. 发明授权

US07937535B2 Managing cache coherency in a data processing apparatus 有权
标题翻译：在数据处理设备中管理高速缓存一致性
公开(公告)号：US07937535B2
公开(公告)日：2011-05-03
申请号：US11709279
申请日：2007-02-22
申请人： Emre Özer , Stuart David Biles , Simon Andrew Ford
发明人： Emre Özer , Stuart David Biles , Simon Andrew Ford
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0831 , G06F12/0822 , Y02D10/13
摘要： Each of plural processing units has a cache, and each cache has indication circuitry containing segment filtering data. The indication circuitry responds to an address specified by an access request from an associated processing unit to reference the segment filtering data to indicate whether the data is either definitely not stored or is potentially stored in that segment. Cache coherency circuitry ensures that data accessed by each processing unit is up-to-date and has snoop indication circuitry whose content is derived from the already-provided segment filtering data. For certain access requests, the cache coherency circuitry initiates a coherency operation during which the snoop indication circuitry determines whether any of the caches requires a snoop operation. For each cache that does, the cache coherency circuitry issues a notification to that cache identifying the snoop operation to be performed.
摘要翻译：多个处理单元中的每一个具有高速缓存，并且每个高速缓存具有包含段过滤数据的指示电路。指示电路响应来自相关联的处理单元的访问请求指定的地址以引用段过滤数据，以指示数据是否被明确地不存储或潜在地存储在该段中。高速缓存一致性电路确保每个处理单元访问的数据是最新的，并且具有其内容源自已经提供的段过滤数据的窥探指示电路。对于某些访问请求，高速缓存一致性电路发起一致性操作，在此期间，窥探指示电路确定是否有任何缓存需要窥探操作。对于每个缓存，高速缓存一致性电路向该缓存发出一个通知，用于标识要执行的侦听操作。

5. 发明申请

US20090044086A1 Error correction in a set associative storage device 有权
标题翻译：集合关联存储设备中的纠错
公开(公告)号：US20090044086A1
公开(公告)日：2009-02-12
申请号：US12222085
申请日：2008-08-01
申请人： Simon John Craske , Andrew Christopher Rose , Paul Stanley Hughes , Antony John Penton , Richard York , Simon Andrew Ford , Stuart David Biles , Alex James Waugh
发明人： Simon John Craske , Andrew Christopher Rose , Paul Stanley Hughes , Antony John Penton , Richard York , Simon Andrew Ford , Stuart David Biles , Alex James Waugh
IPC分类号： G06F11/30
CPC分类号： G06F11/1064
摘要： A data processing apparatus is provided comprising processing circuitry for performing data processing operations, a set associative storage device for storing data values for access by the processing circuitry when performing data processing operations, error detection circuitry for performing, for each access to the storage device, an error detection operation on the data value accessed, and maintenance circuitry associated with the storage device for performing one or more maintenance operations. The processing circuitry is arranged to issue an error detection maintenance request to the maintenance circuitry specifying at least one specific physical location within the storage device, and the maintenance circuitry is responsive to the error detection maintenance request to perform at least one dummy access to the at least one specific physical location within the storage device and to provide the processing circuitry with error status information derived from the error detection operation performed by the error detection circuitry in respect of said at least one dummy access.
摘要翻译：提供了一种数据处理装置，包括用于执行数据处理操作的处理电路，用于在执行数据处理操作时存储由处理电路进行访问的数据值的组合关联存储装置，用于对存储装置的每次访问执行的错误检测电路，对所访问的数据值的错误检测操作，以及与存储设备相关联的用于执行一个或多个维护操作的维护电路。处理电路被布置为向维护电路发出指示存储设备内的至少一个特定物理位置的错误检测维护请求，并且维护电路响应于错误检测维护请求，以对至少一个虚拟访问在所述存储设备内的至少一个特定的物理位置，并且为所述处理电路提供由所述错误检测电路针对所述至少一个虚拟访问执行的错误检测操作导出的错误状态信息。

6. 发明申请

US20100045682A1 Apparatus and method for communicating between a central processing unit and a graphics processing unit 有权
标题翻译：用于在中央处理单元和图形处理单元之间进行通信的装置和方法
公开(公告)号：US20100045682A1
公开(公告)日：2010-02-25
申请号：US12461418
申请日：2009-08-11
申请人： Simon Andrew Ford , Sean Tristram Ellis , Edward Charles Plowman
发明人： Simon Andrew Ford , Sean Tristram Ellis , Edward Charles Plowman
IPC分类号： G06F15/16 , G06F15/167
CPC分类号： G06F9/3877 , G06F9/30076 , G06F9/30181 , G06F9/30189 , G06F9/3851 , G06T1/20
摘要： The present invention provides an improved technique for communicating between a central processing unit and a graphics processing unit of a data processing apparatus. Shared memory is provided which is accessible by the central processing unit and the graphics processing unit, and via which data structures are shareable between the central processing unit and the graphics processing unit. A bus is also provided via which the central processing unit, graphics processing unit and shared memory communicate. In accordance with a first mechanism of controlling the graphics processing unit, the central processing unit routes control signals via the bus. However, in addition, an interface is provided between the central processing unit and the graphics processing unit, and in accordance with an additional mechanism for controlling the graphics processing unit, the central processing unit provides control signals over the interface. This enables the GPU to continue to be used to handle large batches of graphics processing operations loosely coupled with the operations performed by the CPU, whilst through use of the additional mechanism it is also possible to employ the GPU to perform processing operations on behalf of the CPU in situations where those operations are tightly coupled with the operations performed by the CPU.
摘要翻译：本发明提供了一种用于在数据处理装置的中央处理单元和图形处理单元之间进行通信的改进技术。提供共享存储器，其可由中央处理单元和图形处理单元访问，并且经由该数据结构可在中央处理单元和图形处理单元之间共享。还提供了一个中央处理单元，图形处理单元和共享存储器通信的总线。根据控制图形处理单元的第一机构，中央处理单元经由总线传送控制信号。然而，另外，在中央处理单元和图形处理单元之间提供接口，并且根据用于控制图形处理单元的附加机构，中央处理单元通过接口提供控制信号。这使得GPU能够继续用于处理与CPU执行的操作松散耦合的大量图形处理操作，而通过使用附加机制，还可以使用GPU来代表CPU执行处理操作在这些操作与CPU执行的操作紧密耦合的情况下，CPU。

7. 发明申请

US20080195856A1 Target device programmer 有权
标题翻译：目标设备编程器
公开(公告)号：US20080195856A1
公开(公告)日：2008-08-14
申请号：US11822149
申请日：2007-07-02
申请人： Simon Andrew Ford , Christopher James Styles
发明人： Simon Andrew Ford , Christopher James Styles
IPC分类号： G06F1/00
CPC分类号： G06F17/5054
摘要： A programmer 10 for a target device 16 is provided with a mass storage interface 12 for connecting to a host 2 so as to appear as a mass storage device to the host 2. A target programmer 18 is responsive to an image transferred from the host 2 to the programmer 10 to apply that image to the target device 16.
摘要翻译：用于目标设备16的编程器10设置有大容量存储接口12，用于连接到主机2，以便作为海量存储设备呈现给主机2。目标编程器18响应于从主机2传送到编程器10的图像，以将该图像应用于目标设备16。

8. 发明授权

US09557994B2 Data processing apparatus and method for performing N-way interleaving and de-interleaving operations where N is an odd plural number 有权
标题翻译：数据处理装置和方法，用于执行N为奇数的N次交织和解交织操作
公开(公告)号：US09557994B2
公开(公告)日：2017-01-31
申请号：US12588412
申请日：2009-10-14
申请人： Dominic Hugo Symes , Simon Andrew Ford
发明人： Dominic Hugo Symes , Simon Andrew Ford
IPC分类号： G06F9/30 , G06F9/345 , G06F9/38 , G06F7/48
CPC分类号： G06F9/30021 , G06F7/4812 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30109 , G06F9/30112 , G06F9/30138 , G06F9/3016 , G06F9/30167 , G06F9/30189 , G06F9/345 , G06F9/382 , G06F9/3832 , G06F9/3873 , G06F9/3887 , G06F2207/3828
摘要： A data processing apparatus and method are provided for performing rearrangement operations. The data processing apparatus has a register data store with a plurality of registers, each register storing a plurality of data elements. Processing circuitry is responsive to control signals to perform processing operations on the data elements. An instruction decoder is responsive to at least one but no more than N rearrangement instructions, where N is an odd plural number, to generate control signals to control the processing circuitry to perform a rearrangement process at least equivalent to: obtaining as source data elements the data elements stored in N registers of said register data store as identified by the at least one re-arrangement instruction; performing a rearrangement operation to rearrange the source data elements between a regular N-way interleaved order and a de-interleaved order in order to produce a sequence of result data elements; and outputting the sequence of result data elements for storing in the register data store. This provides a particularly efficient technique for performing N-way interleave and de-interleave operations, where N is an odd number, resulting in high performance, low energy consumption, and reduced register use when compared with known prior art techniques.
摘要翻译：提供了一种执行重排操作的数据处理装置和方法。数据处理装置具有具有多个寄存器的寄存器数据存储器，每个寄存器存储多个数据元素。处理电路响应于控制信号来对数据元素执行处理操作。指令解码器响应于至少一个但不超过N个重排指令，其中N是奇数复数，以产生控制信号，以控制处理电路执行至少等同于：作为源数据元素的重新排列过程存储在由所述至少一个重新布置指令识别的所述寄存器数据存储器的N个寄存器中的数据元素; 执行重排操作以在常规N路交错顺序和解交织顺序之间重新排列源数据元素，以便产生结果数据元素的序列; 并输出用于存储在寄存器数据存储器中的结果数据元素的序列。这提供了一种特别有效的技术，用于执行N路交错和解交织操作，其中N是奇数，导致高性能，低能量消耗和降低的寄存器使用，与已知的现有技术相比。

9. 发明授权

US09405939B2 Data processing on a non-volatile mass storage device 有权
标题翻译：在非易失性大容量存储设备上进行数据处理
公开(公告)号：US09405939B2
公开(公告)日：2016-08-02
申请号：US12285516
申请日：2008-10-07
申请人： Simon Andrew Ford , Christopher James Styles
发明人： Simon Andrew Ford , Christopher James Styles
IPC分类号： G06F15/16 , G06F21/80 , G06F21/56 , G06F21/78 , G06F21/71 , G06F21/12 , H04L29/06
CPC分类号： G06F17/302 , G06F17/30876 , G06F17/30896 , G06F21/123 , G06F21/56 , G06F21/71 , G06F21/78 , G06F21/80 , G06F2221/2129 , H04L63/061
摘要： A non-volatile mass storage device is provided comprising memory circuitry accessible to a host data processing device via a communication link. The non-volatile mass storage device comprises processing circuitry for locally accessing the memory circuitry of the file system and is capable of triggering generation of a file for storage on the memory circuitry by connection of the non-volatile mass storage device to the host data processing device. The generated file comprises information dependent upon a state of the non-volatile mass storage device. A corresponding method of operating a non-volatile mass storage device is provided and a computer program is provided for obtaining the information dependent upon the state of the non-volatile mass storage device, for locally accessing the memory circuitry and for generating the file for storage on the memory circuitry.
摘要翻译：提供了一种非易失性大容量存储装置，其包括经由通信链路可由主机数据处理装置访问的存储器电路。非挥发性大容量存储设备包括用于本地访问文件系统的存储器电路的处理电路，并且能够通过将非易失性大容量存储设备连接到主机数据处理来触发用于存储在存储器电路上的文件的生成设备。所生成的文件包括取决于非易失性大容量存储设备的状态的信息。提供了操作非易失性大容量存储设备的相应方法，并且提供了一种计算机程序，用于根据非易失性大容量存储设备的状态获得信息，用于本地访问存储器电路并生成用于存储的文件在存储器电路上。

10. 发明授权

US08484508B2 Data processing apparatus and method for providing fault tolerance when executing a sequence of data processing operations 有权
标题翻译：用于在执行数据处理操作序列时提供容错的数据处理装置和方法
公开(公告)号：US08484508B2
公开(公告)日：2013-07-09
申请号：US12656068
申请日：2010-01-14
申请人： Antony John Penton , Simon Andrew Ford , Andrew Christopher Rose
发明人： Antony John Penton , Simon Andrew Ford , Andrew Christopher Rose
IPC分类号： G06F11/00
CPC分类号： G06F11/1641
摘要： A data processing apparatus and method provide fault tolerance when executing a sequence of data processing operations. The data processing apparatus has processing circuitry for performing the sequence of data processing operations, and a redundant copy of that processing circuitry for operating in parallel with the processing circuitry, and for performing the same sequence of data processing operations. Error detection circuitry detects an error condition when output data generated by the processing circuitry differs from corresponding output data generated by the redundant copy. Shared prediction circuitry generates predicted data input to both the processing circuitry and the redundant copy, with the processing circuitry and redundant copy then performing speculative processing of one or more data processing operations in dependence on that predicted data. Each of the processing circuitry and the redundant copy include checking circuitry for determining whether the speculative processing was correct, and initiating corrective action if the speculative processing was not correct. By sharing the prediction circuitry rather than replicating it within both the processing circuitry and the redundant copy, significant area and power consumption benefits can be achieved without affecting the ability of the apparatus to detect faults.
摘要翻译：数据处理装置和方法在执行数据处理操作的序列时提供容错。数据处理装置具有用于执行数据处理操作序列的处理电路，以及用于与处理电路并联操作并用于执行相同数据处理操作序列的该处理电路的冗余副本。当由处理电路产生的输出数据与由冗余副本产生的相应输出数据不同时，错误检测电路检测错误状况。共享预测电路产生输入到处理电路和冗余副本的预测数据，处理电路和冗余副本然后根据该预测数据执行一个或多个数据处理操作的推测处理。处理电路和冗余副本中的每一个包括用于确定推测性处理是否正确的检查电路，以及如果推测性处理不正确则启动校正动作。通过共享预测电路而不是在处理电路和冗余副本中进行复制，可以在不影响设备检测故障的能力的情况下实现显着的面积和功耗优点。

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