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1. 发明专利

JP2007234009A Simultaneous code checker and hardware efficient high-speed i/o having built-in self-test and debug function 有权
标题翻译：具有内置自检和调试功能的同时代码检查器和硬件有效的高速I / O
公开(公告)号：JP2007234009A
公开(公告)日：2007-09-13
申请号：JP2007037099
申请日：2007-01-19
申请人： Silicon Image Inc , シリコンイメージ,インコーポレイテッド
发明人： SUL CHINSONG , CHOI HOON , AHN GIJUNG
IPC分类号： G06F13/00
CPC分类号： H03M5/00 , G11B2020/1438 , H03M13/09 , H03M13/33 , H04L25/491
摘要： PROBLEM TO BE SOLVED: To provide a system, an apparatus and a method for testing about a high-speed data transmission error. SOLUTION: The method, the apparatus and the system for testing an error in a high-speed input-output system are available. The system and the apparatus include a simultaneous code checker for testing the error in an encoded data packet through a static characteristic of a data packet and a dynamic characteristic of a data stream including a packet. The method sometimes takes a step to detect an invalid encoded packet by using the static characteristic of the data packet and the dynamic characteristic of the data stream including the packet. The method for optimizing a design of a simultaneous code checker logic uses an unspecified condition, and a simultaneous code checker circuit reduces a logic element and a semiconductor area requirement. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于测试高速数据传输错误的系统，装置和方法。解决方案：用于测试高速输入输出系统中的错误的方法，装置和系统是可用的。该系统和装置包括同时代码检查器，用于通过数据分组的静态特性和包括分组的数据流的动态特性来测试编码数据分组中的错误。该方法有时通过使用数据分组的静态特性和包括分组的数据流的动态特性来检测无效编码分组。用于优化同时代码检查器逻辑的设计的方法使用未指定的条件，并且同时代码检查器电路减少了逻辑元件和半导体区域要求。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2014102254A Circuit to prevent peak power problems during scan shift 审中-公开
标题翻译：在扫描转换期间防止峰值电源问题的电路
公开(公告)号：JP2014102254A
公开(公告)日：2014-06-05
申请号：JP2014000591
申请日：2014-01-06
申请人： Silicon Image Inc , シリコンイメージ,インコーポレイテッド
发明人： SUL CHINSONG , KIM HEON
IPC分类号： G01R31/28
CPC分类号： G01R31/318575 , G01R31/318594
摘要： PROBLEM TO BE SOLVED: To provide scanning technics.SOLUTION: A chip comprises first and second scan chain segments, and each segment comprises registers and multiplexers to provide scan input signals to the registers during a scan input period and captured output signals during a capture period. The chip also comprises a circuit to provide first and second test clock signals to the registers of the first and second scan chain segments, respectively. The second test clock signal is provided by a signal path in the circuit during the scan input period different from a signal path during the capture period, and during the scan input period a second test clock signal is skewed with respect to a first test clock signal. Other embodiments are described and claimed.
摘要翻译：要解决的问题：提供扫描技术。解决方案：芯片包括第一和第二扫描链段，每个段包括寄存器和多路复用器，以在扫描输入周期期间向寄存器提供扫描输入信号，并且在捕获周期期间捕获输出信号。芯片还包括分别向第一和第二扫描链段的寄存器提供第一和第二测试时钟信号的电路。第二测试时钟信号由在捕获周期期间与信号路径不同的扫描输入周期期间的电路中的信号路径提供，并且在扫描输入周期期间，第二测试时钟信号相对于第一测试时钟信号偏斜。描述和要求保护其他实施例。

3. 发明专利

JP2008051804A Test clock control structure to generate configurable test clock for scan-based testing of electronic circuits using programmable test clock controller 有权
标题翻译：使用可编程测试时钟控制器生成可配置测试时钟的测试时钟控制结构用于基于扫描的电子电路测试
公开(公告)号：JP2008051804A
公开(公告)日：2008-03-06
申请号：JP2007181485
申请日：2007-06-13
申请人： Silicon Image Inc , シリコンイメージ,インコーポレイテッド
发明人： SUL CHINSONG
IPC分类号： G01R31/28 , G06F11/22 , H01L21/822 , H01L27/04 , H03K19/173
CPC分类号： G01R31/318552 , G01R31/318541 , G01R31/318594 , G01R31/31922
摘要： PROBLEM TO BE SOLVED: To disclose a system, structure and method for performing scan-based testing of electronic circuits by generating a test clock for scan chains. SOLUTION: A test clock control structure includes a programmable test clock controller. The programmable test clock controller includes a test clock generator for generating a configurable test clock. The controller also includes a scan layer interface driving a scan chain portion with the configurable test clock, and a control layer interface configured so as to access the control information for controlling the scan chain portion. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：公开通过生成扫描链的测试时钟来执行电子电路的基于扫描的测试的系统，结构和方法。
解决方案：测试时钟控制结构包括可编程测试时钟控制器。可编程测试时钟控制器包括用于产生可配置测试时钟的测试时钟发生器。所述控制器还包括驱动具有所述可配置测试时钟的扫描链部分的扫描层接口以及被配置为访问所述控制信息以控制所述扫描链部分的控制层接口。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2008014950A Scan base test of device provided with test clock control structure 有权
标题翻译：具有测试时钟控制结构的器件的扫描基准测试
公开(公告)号：JP2008014950A
公开(公告)日：2008-01-24
申请号：JP2007181486
申请日：2007-06-13
申请人： Silicon Image Inc , シリコンイメージ,インコーポレイテッド
发明人： SUL CHINSONG
IPC分类号： G01R31/28 , G06F11/22
CPC分类号： G01R31/318552 , G01R31/318594 , G01R31/31937
摘要： PROBLEM TO BE SOLVED: To disclose a method for performing a scan base test on a circuit using one or more test clock control structures, and a computer readable medium. SOLUTION: This method includes a step of performing a test in a domain and implementing a first subset of a domain of a plurality of circuits provided with a dynamic defect detection test pattern. This method also includes a step of performing a test among the domains and implementing a second subset of the domain of the plurality of circuits provided with the dynamic defect detection test pattern. The dynamic defect detection test pattern can contain a last-shift-launch test pattern and a broad-side test pattern, for example. This method can include a step of constituting different programmable test clock controllers so that different clock domains may be tested mostly in parallel. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：公开一种使用一个或多个测试时钟控制结构对电路进行扫描基础测试的方法和计算机可读介质。解决方案：该方法包括在域中执行测试并实现具有动态缺陷检测测试模式的多个电路的域的第一子集的步骤。该方法还包括在域之间执行测试并实现具有动态缺陷检测测试模式的多个电路的域的第二子集的步骤。例如，动态缺陷检测测试模式可以包含最后移动发射测试模式和宽侧测试模式。该方法可以包括构成不同的可编程测试时钟控制器的步骤，使得可以并行测试不同的时钟域。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2008122399A Interface testing circuit and method 有权
标题翻译：接口测试电路和方法
公开(公告)号：JP2008122399A
公开(公告)日：2008-05-29
申请号：JP2007322609
申请日：2007-11-15
申请人： Silicon Image Inc , シリコンイメージ,インコーポレイテッド
发明人： SUL CHINSONG , KIM HEON C , AHN GIJUNG
IPC分类号： G01R31/3183 , G01R31/28
CPC分类号： H04L1/245
摘要： PROBLEM TO BE SOLVED: To provide an interface test circuit and a method including a high-speed input/output circuit (HSIO) test circuit and method which can be used for assembled self-test (BIST).
SOLUTION: In one embodiment, a device comprises a conductor, and a transmitter including a transmitter test circuit which embeds test characteristics in a test pattern signal and transmits the test pattern signal to the conductor. Also in one embodiment, the device comprises the conductor which conveys the test pattern which has the embedded test characteristics, and a receiver test circuit which judges whether the test pattern signal is received, and test characteristics are extracted, and extracted test characteristics adapt a predetermined test characteristics. Other embodiments are indicated by the specifications and claims.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种可用于组装自检（BIST）的接口测试电路和包括高速输入/输出电路（HSIO）测试电路和方法的方法。解决方案：在一个实施例中，设备包括导体和发射器，其包括发射器测试电路，其将测试特性嵌入测试图案信号中，并将测试图案信号传输到导体。同样在一个实施例中，该装置包括传送具有嵌入测试特性的测试图案的导体，以及一个接收器测试电路，用于判断是否接收到测试图案信号，并提取测试特征，并且提取的测试特性使预定的测试特性。其他实施例由说明书和权利要求书指出。版权所有（C）2008，JPO＆INPIT

6. 发明专利

DE602007003052D1 未知
公开(公告)号：DE602007003052D1
公开(公告)日：2009-12-17
申请号：DE602007003052
申请日：2007-06-25
申请人： SILICON IMAGE INC
发明人： SUL CHINSONG
IPC分类号： G01R31/3185 , G01R31/319 , G06F11/27
摘要： Systems, structures and methods for generating a test clock for scan chains to implement scan-based testing of electronic circuits are disclosed. In one embodiment, a test clock control structure includes a programmable test clock controller. The programmable test clock controller includes a test clock generator for generating a configurable test clock. It also includes a scan layer interface to drive a scan chain portion with the configurable test clock, and a control layer interface configured to access control information for controlling the scan chain portion. In another embodiment, a method effectuates scan-based testing of circuits. The method includes performing at least one intra-domain test and performing at least one inter-domain test using implementing dynamic fault detection test patterns, which can include last-shift-launch test patterns and broadside test patterns.

7. 发明专利

DE602007011840D1 Simultaner Codeprüfer und hardware-effiziente Eingabe/Ausgabe mit hoher Geschwindigkeit mit eingebautem Selbsttest und Fehlerbeseitigungsfunktionen 未知
公开(公告)号：DE602007011840D1
公开(公告)日：2011-02-24
申请号：DE602007011840
申请日：2007-01-19
申请人： SILICON IMAGE INC
发明人： SUL CHINSONG , CHOI HOON , AHN GIJUNG
IPC分类号： H03M13/21 , H03M13/09 , H03M13/33

8. 发明专利

AT528654T 未知
公开(公告)号：AT528654T
公开(公告)日：2011-10-15
申请号：AT08705457
申请日：2008-01-02
申请人： SILICON IMAGE INC
发明人： SUL CHINSONG , KIM HEON
IPC分类号： G01R31/3185
摘要： In some embodiments, a chip includes first and second scan chain segments each including registers and multiplexers to provide to the registers scan input signals during scan input periods and captured output signals during a capture periods. The chip also includes circuitry to provide first and second test clock signals to the registers of the first and second scan chain segments, respectively, wherein the second test clock signal is provided by a different signal path in the circuitry during the scan input periods than during the capture periods, and during the scan input periods the second test clock signal is skewed with respect to the first test clock signal. Other embodiments are described and claimed.

9. 发明专利

DE602007009170D1 Schnittstellentestschaltung und Verfahren 未知
公开(公告)号：DE602007009170D1
公开(公告)日：2010-10-28
申请号：DE602007009170
申请日：2007-10-31
申请人： SILICON IMAGE INC
发明人： SUL CHINSONG , KIM HEON C , AHN GIJUNG
IPC分类号： H04L1/24

10. 发明专利

DE602007003050D1 未知
公开(公告)号：DE602007003050D1
公开(公告)日：2009-12-17
申请号：DE602007003050
申请日：2007-06-25
申请人： SILICON IMAGE INC
发明人： SUL CHINSONG
IPC分类号： G01R31/3185 , G01R31/319 , G06F11/27
摘要： Methods and computer readable media for performing scan-based testing of circuits using one or more test clock control structures are disclosed. In one embodiment, a method includes performing an intra-domain test to exercise a first subset of domains of the plurality of circuits implementing dynamic fault detection test patterns. It also includes performing an inter-domain test to exercise a second subset of domains of the plurality of circuits implementing dynamic fault detection test patterns. The dynamic fault detection test patterns can include, for example, last-shift-launch test patterns and broadside test patterns. In various embodiments, the method can include configuring different programmable test clock controllers to test different domains substantially in parallel.

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