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1. 发明申请

US20130043527A1 SHIELDED GATE TRENCH MOSFET PACKAGE 有权
标题翻译：屏蔽栅极晶体管封装
公开(公告)号：US20130043527A1
公开(公告)日：2013-02-21
申请号：US13212940
申请日：2011-08-18
申请人： SIK LUI , Yi Su , Daniel Ng , Daniel Calafut , Anup Bhalla
发明人： SIK LUI , Yi Su , Daniel Ng , Daniel Calafut , Anup Bhalla
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L23/647 , H01L24/06 , H01L24/48 , H01L24/49 , H01L29/407 , H01L29/42368 , H01L29/4238 , H01L29/66734 , H01L29/7803 , H01L29/7811 , H01L2224/0603 , H01L2224/4813 , H01L2224/48247 , H01L2224/4911 , H01L2224/49111 , H01L2924/00014 , H01L2924/10253 , H01L2924/12032 , H01L2924/13091 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A shielded gate trench field effect transistor can be formed on a substrate having an epitaxial layer on the substrate and a body layer on the epitaxial layer. A trench formed in the body layer and epitaxial layer is lined with a dielectric layer. A shield electrode is formed within a lower portion of the trench. The shield electrode is insulated by the dielectric layer. A gate electrode is formed in the trench above the shield electrode and insulated from the shield electrode by an additional dielectric layer. One or more source regions formed within the body layer is adjacent a sidewall of the trench. A source pad formed above the body layer is electrically connected to the one or more source regions and insulated from the gate electrode and shield electrode. The source pad provides an external contact to the source region. A gate pad provides an external contact to the gate electrode. A shield electrode pad provides an external contact to the shield electrode. A resistive element can be electrically connected between the shield electrode pad and the source lead in the package.
摘要翻译：可以在衬底上具有外延层的衬底上形成屏蔽栅沟槽场效应晶体管，并在外延层上形成体层。形成在体层和外延层中的沟槽衬有介电层。屏蔽电极形成在沟槽的下部内。屏蔽电极由电介质层绝缘。栅极电极形成在屏蔽电极上方的沟槽中，并通过附加的介电层与屏蔽电极绝缘。形成在体层内的一个或多个源极区域与沟槽的侧壁相邻。形成在主体层上方的源极焊盘与一个或多个源极区域电连接并与栅电极和屏蔽电极绝缘。源极焊盘提供与源极区域的外部接触。栅极焊盘提供与栅电极的外部接触。屏蔽电极焊盘提供与屏蔽电极的外部接触。电阻元件可以电连接在封装中的屏蔽电极焊盘和源极引线之间。

2. 发明授权

US08829603B2 Shielded gate trench MOSFET package 有权
标题翻译：屏蔽栅沟MOSFET封装
公开(公告)号：US08829603B2
公开(公告)日：2014-09-09
申请号：US13212940
申请日：2011-08-18
申请人： Sik Lui , Yi Su , Daniel Ng , Daniel Calafut , Anup Bhalla
发明人： Sik Lui , Yi Su , Daniel Ng , Daniel Calafut , Anup Bhalla
IPC分类号： H01L29/66 , H01L23/64 , H01L29/78 , H01L29/40 , H01L29/423 , H01L23/00
CPC分类号： H01L29/7813 , H01L23/647 , H01L24/06 , H01L24/48 , H01L24/49 , H01L29/407 , H01L29/42368 , H01L29/4238 , H01L29/66734 , H01L29/7803 , H01L29/7811 , H01L2224/0603 , H01L2224/4813 , H01L2224/48247 , H01L2224/4911 , H01L2224/49111 , H01L2924/00014 , H01L2924/10253 , H01L2924/12032 , H01L2924/13091 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A shielded gate trench field effect transistor can be formed on a substrate having an epitaxial layer on the substrate and a body layer on the epitaxial layer. A trench formed in the body layer and epitaxial layer is lined with a dielectric layer. A shield electrode is formed within a lower portion of the trench. The shield electrode is insulated by the dielectric layer. A gate electrode is formed in the trench above the shield electrode and insulated from the shield electrode by an additional dielectric layer. One or more source regions formed within the body layer is adjacent a sidewall of the trench. A source pad formed above the body layer is electrically connected to the one or more source regions and insulated from the gate electrode and shield electrode. The source pad provides an external contact to the source region. A gate pad provides an external contact to the gate electrode. A shield electrode pad provides an external contact to the shield electrode. A resistive element can be electrically connected between the shield electrode pad and the source lead in the package.
摘要翻译：可以在衬底上具有外延层的衬底上形成屏蔽栅沟槽场效应晶体管，并在外延层上形成体层。形成在体层和外延层中的沟槽衬有介电层。屏蔽电极形成在沟槽的下部内。屏蔽电极由电介质层绝缘。栅极电极形成在屏蔽电极上方的沟槽中，并通过附加的介电层与屏蔽电极绝缘。形成在体层内的一个或多个源极区域与沟槽的侧壁相邻。形成在主体层上方的源极焊盘与一个或多个源极区域电连接并与栅电极和屏蔽电极绝缘。源极焊盘提供与源极区域的外部接触。栅极焊盘提供与栅电极的外部接触。屏蔽电极焊盘提供与屏蔽电极的外部接触。电阻元件可以电连接在封装中的屏蔽电极焊盘和源极引线之间。

3. 发明申请

US20140151790A1 APPROACH TO INTEGRATE SCHOTTKY IN MOSFET 有权
标题翻译：在MOSFET中整合肖特基的方法
公开(公告)号：US20140151790A1
公开(公告)日：2014-06-05
申请号：US13873017
申请日：2013-04-29
申请人： Sik Lui , Yi Su , Daniel Ng , Anup Bhalla
发明人： Sik Lui , Yi Su , Daniel Ng , Anup Bhalla
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7806 , H01L27/0629 , H01L29/0619 , H01L29/0623 , H01L29/1095 , H01L29/41766 , H01L29/66734 , H01L29/7813 , H01L29/872 , H01L29/8725
摘要： An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions.
摘要翻译：集成结构结合了场效应晶体管和肖特基二极管。形成衬底组合物的沟槽沿其中形成台面的衬底组合物的深度延伸。每个沟槽填充有导电材料，该导电材料通过形成栅极区域的电介质材料与沟槽壁分离。每个台面形状内部的两个第一导电类型体区部分地沉积到基底组合物的深度中。衬底组合物的暴露部分分离身体区域。每个身体区域内的第二导电类型源区域与每个孔的相邻侧和相邻侧相邻。每个孔内的肖特基势垒金属在分离体区的基底组合物的暴露部分的暴露的垂直侧壁的界面处形成肖特基结。

4. 发明授权

US08431470B2 Approach to integrate Schottky in MOSFET 有权
标题翻译：将肖特基集成在MOSFET中的方法
公开(公告)号：US08431470B2
公开(公告)日：2013-04-30
申请号：US13079675
申请日：2011-04-04
申请人： Sik Lui , Yi Su , Daniel Ng , Anup Bhalla
发明人： Sik Lui , Yi Su , Daniel Ng , Anup Bhalla
IPC分类号： H01L21/28 , H01L21/02
CPC分类号： H01L29/7806 , H01L27/0629 , H01L29/0619 , H01L29/0623 , H01L29/1095 , H01L29/41766 , H01L29/66734 , H01L29/7813 , H01L29/872 , H01L29/8725
摘要： An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions.
摘要翻译：集成结构结合了场效应晶体管和肖特基二极管。形成衬底组合物的沟槽沿其中形成台面的衬底组合物的深度延伸。每个沟槽填充有导电材料，该导电材料通过形成栅极区域的电介质材料与沟槽壁分离。每个台面形状内部的两个第一导电类型体区部分地沉积到基底组合物的深度中。衬底组合物的暴露部分分离身体区域。每个身体区域内的第二导电类型源区域与每个孔的相邻侧和相邻侧相邻。每个孔内的肖特基势垒金属在分离体区的基底组合物的暴露部分的暴露的垂直侧壁的界面处形成肖特基结。

5. 发明申请

US20120248530A1 APPROACH TO INTERGRATE SCHOTTKY IN MOSFET 有权
标题翻译：将肖特考虑在MOSFET中的方法
公开(公告)号：US20120248530A1
公开(公告)日：2012-10-04
申请号：US13079675
申请日：2011-04-04
申请人： Sik Lui , Yi Su , Daniel Ng , Anup Bhalla
发明人： Sik Lui , Yi Su , Daniel Ng , Anup Bhalla
IPC分类号： H01L29/78 , H01L29/872 , H01L21/8234
CPC分类号： H01L29/7806 , H01L27/0629 , H01L29/0619 , H01L29/0623 , H01L29/1095 , H01L29/41766 , H01L29/66734 , H01L29/7813 , H01L29/872 , H01L29/8725
摘要： An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions.
摘要翻译：集成结构结合了场效应晶体管和肖特基二极管。形成衬底组合物的沟槽沿其中形成台面的衬底组合物的深度延伸。每个沟槽填充有导电材料，该导电材料通过形成栅极区域的电介质材料与沟槽壁分离。每个台面形状内部的两个第一导电类型体区部分地沉积到基底组合物的深度中。衬底组合物的暴露部分分离身体区域。每个身体区域内的第二导电类型源区域与每个孔的相邻侧和相邻侧相邻。每个孔内的肖特基势垒金属在分离体区的基底组合物的暴露部分的暴露的垂直侧壁的界面处形成肖特基结。

6. 发明授权

US09620498B2 Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection 有权
公开(公告)号：US09620498B2
公开(公告)日：2017-04-11
申请号：US14341789
申请日：2014-07-26
申请人： Yi Su , Anup Bhalla , Daniel Ng
发明人： Yi Su , Anup Bhalla , Daniel Ng
IPC分类号： H01L27/02 , H01L27/06
CPC分类号： H01L27/0255 , H01L27/0629
摘要： A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped-well that is disposed below and engulfing the U-shaped bend.

7. 发明申请

US20160027771A1 CONFIGURATION OF GATE TO DRAIN (GD) CLAMP AND ESD PROTECTION CIRCUIT FOR POWER DEVICE BREAKDOWN PROTECTION 审中-公开
标题翻译：闸门配置（GD）钳位和防静电保护电路，用于电源设备断开保护
公开(公告)号：US20160027771A1
公开(公告)日：2016-01-28
申请号：US14341789
申请日：2014-07-26
申请人： Yi Su , Anup Bhalla , Daniel Ng
发明人： Yi Su , Anup Bhalla , Daniel Ng
IPC分类号： H01L27/02 , H01L27/06
CPC分类号： H01L27/0255 , H01L27/0629
摘要： A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped-well that is disposed below and engulfing the U-shaped bend.
摘要翻译：一种半导体功率器件，其被支撑在半导体衬底上，该半导体衬底包括多个晶体管单元，每个晶体管单元具有源极和漏极，栅极用于控制在源极和漏极之间传输的电流。半导体还包括在栅极和漏极之间串联连接的栅极 - 漏极（GD）钳位端接器，还包括串联连接到硅二极管的多个背对背多晶硅二极管，包括半导体中的并行掺杂的列衬底，其中平行掺杂的柱具有预定的间隙。掺杂的柱还包括U形弯曲柱，其将平行掺杂的柱的端部连接在一起，深深的掺杂阱被设置在U形弯曲部的下方并且被吞噬。

8. 发明申请

US20110227155A1 INTEGRATION OF A SENSE FET INTO A DISCRETE POWER MOSFET 有权
标题翻译：将感测FET集成到分立功率MOSFET中
公开(公告)号：US20110227155A1
公开(公告)日：2011-09-22
申请号：US13149051
申请日：2011-05-31
申请人： Yi Su , Anup Bhalla , Daniel Ng
发明人： Yi Su , Anup Bhalla , Daniel Ng
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/8234 , H01L27/088 , H01L29/0646 , H01L29/0653 , H01L29/0696 , H01L29/66734 , H01L29/7815 , H01L2224/0603 , H01L2924/13091 , H01L2924/00
摘要： A main FET and one or more sense FETs are formed in a common substrate. The main FET and sense FET(s) include a source terminal, a gate terminal and a drain terminal. The common gate pad connects the gate terminals of the main FET and sense FET(s). An electrical isolation may be between the gate terminals of the main FET and the sense FET(s). A sense pad in electrical contact with the source of the one or more sense FETs does not overlap an area of the device containing the sense FET(s). It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：主FET和一个或多个感测FET形成在公共衬底中。主FET和感测FET包括源极端子，栅极端子和漏极端子。公共栅极焊盘连接主FET和检测FET的栅极端子。电隔离可以在主FET的栅极端子和感测FET之间。与一个或多个感测FET的源极电接触的感测焊盘不与包含感测FET的器件的区域重叠。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

9. 发明申请

US20110076815A1 Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection 有权
标题翻译：降低了具有静电放电（ESD）电路保护功率的MOSFET的掩模配置
公开(公告)号：US20110076815A1
公开(公告)日：2011-03-31
申请号：US12925820
申请日：2010-10-29
申请人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
发明人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
IPC分类号： H01L21/8234
CPC分类号： H01L29/7811 , H01L27/0255 , H01L29/0619 , H01L29/0696 , H01L29/404 , H01L29/66734 , H01L29/7808 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.
摘要翻译：支撑在半导体衬底上的半导体功率器件包括设置在半导体衬底顶部的图案化ESD多晶硅层的第一部分上的静电放电（ESD）保护电路。该半导体功率器件还包括构图的ESD多晶硅层的第二部分，其构成体部注入离子阻挡层，用于阻止注入体离子进入体内注入离子阻挡层下方的半导体衬底。在示例性实施例中，半导体衬底顶部上的静电放电（ESD）多晶硅层进一步覆盖半导体器件边缘上的划线，由此不再需要钝化层制造用于减少图案所需掩模的半导体器件钝化层。

10. 发明授权

US07799646B2 Integration of a sense FET into a discrete power MOSFET 有权
标题翻译：将感测FET集成到分立功率MOSFET中
公开(公告)号：US07799646B2
公开(公告)日：2010-09-21
申请号：US12098970
申请日：2008-04-07
申请人： Yi Su , Anup Bhalla , Daniel Ng
发明人： Yi Su , Anup Bhalla , Daniel Ng
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/8234 , H01L27/088 , H01L29/0646 , H01L29/0653 , H01L29/0696 , H01L29/66734 , H01L29/7815 , H01L2224/0603 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs, and a common gate pad. The main FET and the one or more sense FETs are formed in a common substrate. The main FET and each of the sense FETs include a source terminal, a gate terminal and a drain terminal. The common gate pad connects the gate terminals of the main FET and the one or more sense FETs. An electrical isolation is disposed between the gate terminals of the main FET and the one or more sense FETs. Embodiments of this invention may be applied to both N-channel and P-channel MOSFET devices.
摘要翻译：半导体器件包括主场效应晶体管（FET）和一个或多个感测FET以及公共栅极焊盘。主FET和一个或多个感测FET形成在公共衬底中。主FET和每个感测FET包括源极端子，栅极端子和漏极端子。公共栅极焊盘连接主FET和一个或多个感测FET的栅极端子。在主FET和一个或多个感测FET的栅极端子之间设置电隔离。本发明的实施例可以应用于N沟道和P沟道MOSFET器件。

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