专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06169036A Method for cleaning via openings in integrated circuit manufacturing 有权
标题翻译：集成电路制造中通孔的清洗方法
公开(公告)号：US06169036A
公开(公告)日：2001-01-02
申请号：US09276034
申请日：1999-03-25
申请人： Siddhartha Bhowmik , Joseph William Buckfeller , G. Craig Clabough , Sailesh Mansinh Merchant
发明人： Siddhartha Bhowmik , Joseph William Buckfeller , G. Craig Clabough , Sailesh Mansinh Merchant
IPC分类号： H01L2100
CPC分类号： H01L21/02063 , H01L21/32136 , H01L21/76804 , H01L21/76805 , H01L21/76814 , H01L21/76838
摘要： A method is for cleaning via openings during manufacturing of integrated circuits. The method preferably comprises the steps of sputter cleaning the via opening at least once, and exposing the via opening to a reducing atmosphere at least once. The method may include alternatingly repeating the sputter cleaning and exposing steps. The step of sputter cleaning is preferably performed prior to the step of exposing, and a sputter cleaning may be performed after a last step of exposing the via opening to the reducing atmosphere. In one embodiment, the exposed metal portion comprises a metal compound, such as an oxide. Accordingly, the step of sputter cleaning removes at least a portion of the metal oxide, and the step of exposing comprises reducing at least a portion of the metal oxide. The invention is particularly applicable when the metal interconnection layer is a copper, as copper readily oxides at its exposed surface.
摘要翻译：一种用于在集成电路制造期间通孔的清洁方法。该方法优选地包括以下步骤：将通孔开口至少一次溅射清洗，并将通孔开至少一次暴露于还原气氛。该方法可以包括交替重复溅射清洗和曝光步骤。溅射清洗的步骤优选在曝光步骤之前进行，并且可以在将通孔打开至还原气氛的最后步骤之后进行溅射清洗。在一个实施方案中，暴露的金属部分包括金属化合物，例如氧化物。因此，溅射清洗的步骤除去至少一部分金属氧化物，并且曝光步骤包括还原金属氧化物的至少一部分。当金属互连层是铜时，本发明特别适用，因为铜在其暴露的表面容易氧化。

2. 发明授权

US06720261B1 Method and system for eliminating extrusions in semiconductor vias 有权
公开(公告)号：US06720261B1
公开(公告)日：2004-04-13
申请号：US09586586
申请日：2000-06-02
申请人： Steven Mark Anderson , Siddhartha Bhowmik , Joseph William Buckfeller , Sailesh Mansinh Merchant , Frank Minardi
发明人： Steven Mark Anderson , Siddhartha Bhowmik , Joseph William Buckfeller , Sailesh Mansinh Merchant , Frank Minardi
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , Y02P80/30
摘要： A system and method for eliminating interconnect extrusions in vias that are formed during ionized metal plasma processing. By eliminating interconnect extrusions in vias, reliability failures and yield loss are decreased. The extrusions of interconnect metallization occur while wafers are subject to elevated temperatures that cause the internal stresses in the interconnect metallization to transit from a substantially tensile mode to a substantially compressive mode. By controlling the interconnect temperature to be below the temperature at which the interconnect transits from a tensile to a compressive mode, interconnect extrusions in vias are eliminated. The interconnect temperature is controlled by using an actively cooled pedestal in combination with a low temperature IMP deposition process. In addition, the IMP processing time may also be decreased to limit heating of the interconnect.

3. 发明授权

US06331484B1 Titanium-tantalum barrier layer film and method for forming the same 有权
标题翻译：钛 - 钽阻挡层膜及其形成方法
公开(公告)号：US06331484B1
公开(公告)日：2001-12-18
申请号：US09519193
申请日：2000-03-06
申请人： Siddhartha Bhowmik , Sailesh Mansinh Merchant , Minseok Oh , Pradip Kumar Roy , Sidhartha Sen
发明人： Siddhartha Bhowmik , Sailesh Mansinh Merchant , Minseok Oh , Pradip Kumar Roy , Sidhartha Sen
IPC分类号： H01L214763
CPC分类号： H01L21/76864 , H01L21/76807 , H01L21/76841 , H01L21/76843 , H01L21/76846 , H01L23/53238 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A titanium-tantalum barrier layer film for use in conjunction with an interconnect film such as copper and a method for forming the same provides a relatively titanium rich/tantalum deficient portion adjacent the interface it forms with a dielectric film and a relatively tantalum rich/titanium deficient portion adjacent the interface it forms with a conductive interconnect film formed over the barrier layer film. The titanium rich/tantalum deficient portion provides good adhesion to the dielectric film and the tantalum rich/titanium deficient portion forms a hetero-epitaxial interface with the interconnect film and suppresses the formation of inter-metallic compounds. A single titanium-tantalum film having a composition gradient from top-to-bottom may be formed using various techniques including PVD, CVD, sputter deposition using a sputtering target of homogeneous composition, and sputter deposition using multiple sputtering targets. A composite titanium-tantalum film consists of two separately formed films.
摘要翻译：用于与诸如铜的互连膜一起使用的钛 - 钽阻挡层膜及其形成方法提供了与其形成的界面相邻的富钛/钽缺陷部分，其与介电膜和相对富钽/钛与其形成的界面相邻的缺陷部分与在阻挡层膜上形成的导电互连膜形成。富钛/钽缺陷部分对电介质膜提供良好的粘附性，并且富钽/钛缺陷部分与互连膜形成异质外延界面并抑制金属间化合物的形成。可以使用包括PVD，CVD，使用均匀组合物的溅射靶的溅射沉积以及使用多个溅射靶的溅射沉积的各种技术来形成具有从顶部到底部的组成梯度的单个钛 - 钽膜。复合钛 - 钽薄膜由两个单独形成的薄膜组成。

4. 发明授权

US07071563B2 Barrier layer for interconnect structures of a semiconductor wafer and method for depositing the barrier layer 失效
标题翻译：用于半导体晶片的互连结构的阻挡层和用于沉积阻挡层的方法
公开(公告)号：US07071563B2
公开(公告)日：2006-07-04
申请号：US09967094
申请日：2001-09-28
申请人： Siddhartha Bhowmik , Sailesh Mansinh Merchant , Darrell L. Simpson
发明人： Siddhartha Bhowmik , Sailesh Mansinh Merchant , Darrell L. Simpson
IPC分类号： H01L21/4763
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/76876 , H01L23/485 , H01L2221/1089 , H01L2924/0002 , Y10S438/978 , H01L2924/00
摘要： An interconnect structure of a semiconductor device includes a tungsten plug (14) deposited in a via or contact window (11). A barrier layer (15) separates the tungsten plug (14) from the surface of a dielectric material (16) within which the contact window or via (11) is formed. The barrier layer (15) is a composite of at least two films. The first film formed on the surface of the dielectric material (16) within the via (11) is a tungsten silicide film (12). The second film is a tungsten film (13) formed on the tungsten silicide film (12). A tungsten plug (14) is formed on the tungsten film (13) to complete interconnect structure. The barrier layer (15) is deposited using a sputtering technique performed in a deposition chamber. The chamber includes tungsten silicide target (19) from which the tungsten silicide film (12) is deposited, and a tungsten coil (20) from which the tungsten film (20) is deposited.
摘要翻译：半导体器件的互连结构包括沉积在通孔或接触窗口（11）中的钨插塞（14）。阻挡层（15）将钨插塞（14）与介电材料（16）的形成有接触窗或通孔（11）的表面分开。阻挡层（15）是至少两层的复合材料。形成在通孔（11）内的电介质材料（16）表面上的第一膜是硅化钨膜（12）。第二膜是在硅化钨膜（12）上形成的钨膜（13）。在钨膜（13）上形成钨塞（14）以完成互连结构。使用在沉积室中进行的溅射技术来沉积阻挡层（15）。该室包括沉积硅化钨膜（12）的硅化钨靶（19）和沉积钨膜（20）的钨线圈（20）。

5. 发明授权

US06455418B1 Barrier for copper metallization 有权
标题翻译：铜金属化阻挡层
公开(公告)号：US06455418B1
公开(公告)日：2002-09-24
申请号：US09723557
申请日：2000-11-28
申请人： Siddhartha Bhowmik , Sailesh Chittipeddi , Sailesh Mansinh Merchant
发明人： Siddhartha Bhowmik , Sailesh Chittipeddi , Sailesh Mansinh Merchant
IPC分类号： H01L214763
CPC分类号： H01L21/76846 , H01L21/76843 , H01L21/76877 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The invention includes a process for copper metallization of an integrated circuit, comprising the steps of forming tantalum on a substrate, forming tantalum nitride over the tantalum, forming titanium nitride over the tantalum nitride, forming copper over the titanium nitride and integrated circuits made thereby. The invention is particularly useful in forming damascene structures with large aspect ratios.
摘要翻译：本发明包括一种用于集成电路的铜金属化的方法，包括在衬底上形成钽的步骤，在钽上形成氮化钽，在氮化钽上形成氮化钛，在氮化钛上形成铜并在其上形成集成电路。本发明特别可用于形成具有大纵横比的镶嵌结构。

6. 发明授权

US06288449B1 Barrier for copper metallization 有权
标题翻译：铜金属化阻挡层
公开(公告)号：US06288449B1
公开(公告)日：2001-09-11
申请号：US09218649
申请日：1998-12-22
申请人： Siddhartha Bhowmik , Sailesh Chittipeddi , Sailesh Mansinh Merchant
发明人： Siddhartha Bhowmik , Sailesh Chittipeddi , Sailesh Mansinh Merchant
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , H01L21/76843 , H01L21/76877 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The invention includes a process for copper metallization of an integrated circuit, comprising the steps of forming tantalum on a substrate, forming tantalum nitride over the tantalum, forming titanium nitride over the tantalum nitride, forming copper over the titanium nitride and integrated circuits made thereby. The invention is particularly useful in forming damascene structures with large aspect ratios.
摘要翻译：本发明包括一种用于集成电路的铜金属化的方法，包括在衬底上形成钽的步骤，在钽上形成氮化钽，在氮化钽上形成氮化钛，在氮化钛上形成铜，并由此制成集成电路。本发明特别可用于形成具有大纵横比的镶嵌结构。

7. 发明授权

US08585180B2 Protective coating for print head feed slots 有权
标题翻译：打印头进纸槽的保护涂层
公开(公告)号：US08585180B2
公开(公告)日：2013-11-19
申请号：US13389709
申请日：2009-10-28
申请人： Siddhartha Bhowmik , Rio Rivas , Gerald R. Wonnacott
发明人： Siddhartha Bhowmik , Rio Rivas , Gerald R. Wonnacott
IPC分类号： B41J2/135
CPC分类号： B41J2/135 , B41J2/1404 , B41J2/1603 , B41J2/1623 , B41J2/1628 , B41J2/1629 , B41J2/1631 , B41J2/1646 , B41J2/17563
摘要： A method of method of making a corrosion resistant print head die comprises creating a self-ionized plasma (SIP) of a coating material; establishing a bias on a print head die comprising a plurality of feed slots (40), each feed slot (40) comprising side wall surfaces (61); and causing the coating material plasma to be deposited on the surfaces to form a protective coating, wherein at least a portion of the coating material is deposited on at least a portion of the surfaces by resputtering. In some cases, the feed slots have an aspect ratio greater than 2. In some cases, the feed slot comprises at least one rib (41), each rib (41) comprising a top surface (68), two side surfaces (66), and an under surface (69), and the formed protective coating is deposited on the top surface (68), two side surfaces (66), and under surface (69) of each rib (41).
摘要翻译：一种制造耐腐蚀印刷头模头的方法包括制造涂覆材料的自离子等离子体（SIP）; 在包括多个进料槽（40）的打印头模头上建立偏压，每个进料槽（40）包括侧壁表面（61）; 并且使涂层材料等离子体沉积在表面上以形成保护涂层，其中至少一部分涂层材料通过再溅射沉积在表面的至少一部分上。在一些情况下，进料槽包括至少一个肋（41），每个肋（41）包括顶表面（68），两个侧表面（66）和下表面（69），并且形成的保护涂层沉积在每个肋（41）的顶表面（68），两个侧表面（66）和下表面（69）处。

8. 发明授权

US08240828B2 Fluid ejection cartridge and method 有权
标题翻译：流体喷射墨盒和方法
公开(公告)号：US08240828B2
公开(公告)日：2012-08-14
申请号：US12747629
申请日：2008-01-09
申请人： Alok Sharan , Manishi Giri , Siddhartha Bhowmik , Richard W Seaver
发明人： Alok Sharan , Manishi Giri , Siddhartha Bhowmik , Richard W Seaver
IPC分类号： B41J2/175
CPC分类号： B41J2/1623 , B41J2/16 , B41J2/1628 , B41J2/1629 , B41J2/1632 , B41J2/1634 , Y10T156/1064
摘要： A fluid ejection cartridge includes a body, having fluid passageways at a first spacing, a die, having fluid passage-ways at a second closer spacing, and an interposer, bonded to the body at a first surface and plasma bonded to the die at a second surface. The interposer includes fluid passageways between the first and second surfaces, which are substantially aligned with the respective passageways of the body and the die.
摘要翻译：流体喷射盒包括具有第一间隔的流体通道的主体，具有第二更靠近间隔的流体通道的模具和在第一表面处结合到主体的中介层，并且在第二面。插入器包括在第一和第二表面之间的流体通道，其基本上与主体和模具的相应通道对准。

9. 发明申请

US20090096845A1 PRINT HEAD DIE SLOT RIBS 有权
标题翻译：打印头DIE槽RIBS
公开(公告)号：US20090096845A1
公开(公告)日：2009-04-16
申请号：US11872701
申请日：2007-10-15
申请人： David M. Braun , Siddhartha Bhowmik , Swaroop K. Kommera , Richard J. Oram , Phillip G. Rourke , Joshua W. Smith , Christopher C. Aschoff
发明人： David M. Braun , Siddhartha Bhowmik , Swaroop K. Kommera , Richard J. Oram , Phillip G. Rourke , Joshua W. Smith , Christopher C. Aschoff
IPC分类号： B41J2/175
CPC分类号： B41J2/1404 , B41J2/14145 , B41J2/1603 , B41J2/1628 , B41J2/1629 , B41J2/1631 , B41J2/1634 , Y10T29/49401
摘要： Methods and an apparatus are disclosed, wherein a print head die includes a slot and ribs across the slot. The ribs are recessed from one or both sides of the die.
摘要翻译：公开了一种方法和装置，其中打印头模具包括穿过狭槽的槽和肋。肋从模具的一侧或两侧凹入。

10. 发明申请

US20090032935A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20090032935A1
公开(公告)日：2009-02-05
申请号：US11831699
申请日：2007-07-31
申请人： Siddhartha Bhowmik , Steven E. Kelly
发明人： Siddhartha Bhowmik , Steven E. Kelly
IPC分类号： H01L23/12 , B41J2/05 , H01L21/02
CPC分类号： B81B3/0072 , B41J2/1601 , B41J2/1628 , B41J2/1629 , B41J2/1642 , B81B2201/052
摘要： Embodiments of a semiconductor device are disclosed.
摘要翻译：公开了半导体器件的实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式