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1. 发明授权

US5719533A Function generator 失效
标题翻译：函数发生器
公开(公告)号：US5719533A
公开(公告)日：1998-02-17
申请号：US721291
申请日：1996-09-26
申请人： Shuji Shibuya , Hisato Takeuchi , Makoto Eguchi , Takaharu Saeki
发明人： Shuji Shibuya , Hisato Takeuchi , Makoto Eguchi , Takaharu Saeki
IPC分类号： H03L1/02 , H03B5/04 , H03B5/32 , H03K3/011
CPC分类号： H03L1/022
摘要： In order to realize highly accurate temperature compensation of a crystal oscillation frequency, a current in proportion to the cube of a difference between an ambient temperature T.sub.a and a reference temperature T.sub.0 is generated. For this purpose, provided are a first series circuit of two diodes; a second series circuit of three diodes; a third series circuit of two diodes; a fourth series circuit of three diodes; a current source for allowing a constant current to flow into the first series circuit; a current source for allowing a constant current to flow from the third series circuit; a current source for allowing a current in proportion to T.sub.a -T.sub.0 to flow into the second series circuit when T.sub.a .gtoreq.T.sub.0 and allowing a current in proportion to .vertline.T.sub.a -T.sub.0 .vertline. to flow from the fourth series circuit when T.sub.a
摘要翻译：为了实现高精度的晶体振荡频率的温度补偿，产生与环境温度Ta和参考温度T0之间的差的立方成比例的电流。为此，提供了两个二极管的第一串联电路; 三个二极管的第二个串联电路; 两个二极管的第三个串联电路; 三极二极管的第四个串联电路; 用于允许恒定电流流入第一串联电路的电流源; 用于允许恒定电流从第三串联电路流动的电流源; 当Ta> / = T0时允许与Ta-T0成比例的电流流入第二串联电路的电流源，并允许与| Ta-T0 |成比例的电流; 当Ta

2. 发明授权

US06292066B1 Function generator, crystal oscillation device and method of adjusting crystal oscillation device 有权
标题翻译：函数发生器，晶体振荡装置及调整晶体振荡装置的方法
公开(公告)号：US06292066B1
公开(公告)日：2001-09-18
申请号：US09462564
申请日：2000-06-05
申请人： Shuji Shibuya , Hisato Takeuchi , Junichi Matsuura , Yuichi Tateyama , Takaharu Saeki
发明人： Shuji Shibuya , Hisato Takeuchi , Junichi Matsuura , Yuichi Tateyama , Takaharu Saeki
IPC分类号： H03L102
CPC分类号： G06G7/26 , H03B5/362 , H03B5/368 , H03B2201/0208 , H03L1/022 , H03L1/025 , H03L1/026 , H03L1/028
摘要： A temperature compensating crystal oscillation device includes a constant voltage circuit (12) for outputting a predetermined voltage independent of the ambient temperature, a temperature sensor circuit (13) for outputting a voltage in proportion to the ambient temperature, and a control circuit (14) for receiving the constant voltage output from the constant voltage circuit (12) and the voltage output in proportion to the temperature from the temperature sensor circuit (13) and for generating a control voltage (Vc) used for compensating a temperature characteristic of a quartz oscillator in the entire range of the ambient temperature through polygonal lines approximation of a negative cubic curve by using continuous lines. Furthermore, the crystal oscillation device includes a VCXO (15) whose oscillation frequency is controlled to be a predetermined value by the control voltage (Vc), and a ROM/RAM circuit (16) for storing temperature compensating parameters used for compensation of a temperature characteristic of the control voltage (Vc) for optimizing the oscillation frequency of the VCXO (15).
摘要翻译：温度补偿晶体振荡装置包括用于输出与环境温度无关的预定电压的恒压电路（12），用于输出与环境温度成比例的电压的温度传感器电路（13），以及控制电路（14）用于接收来自恒压电路（12）的恒定电压输出和与温度传感器电路（13）的温度成比例的电压输出，并产生用于补偿石英振荡器（13）的温度特性的控制电压（Vc）在环境温度的整个范围内通过使用连续线的负三次曲线的折线近似。此外，晶体振荡装置包括通过控制电压（Vc）将振荡频率控制为规定值的VCXO（15），以及用于存储用于补偿温度的温度补偿参数的ROM / RAM电路（16）用于优化VCXO（15）的振荡频率的控制电压（Vc）的特性。

3. 发明申请

US20120076246A1 AUTOMATIC GAIN CONTROL DEVICE AND ELECTRONIC DEVICE 审中-公开
标题翻译：自动增益控制装置和电子装置
公开(公告)号：US20120076246A1
公开(公告)日：2012-03-29
申请号：US13309077
申请日：2011-12-01
申请人： Eiji Okada , Satoshi Tsukamoto , Yasuo Oba , Takaharu Saeki
发明人： Eiji Okada , Satoshi Tsukamoto , Yasuo Oba , Takaharu Saeki
IPC分类号： H03G3/20 , H04N5/455 , H04L27/06
CPC分类号： H03G3/3068 , H04B1/18
摘要： An automatic gain control device includes amplifiers cascaded, each having a variable gain; level measurement portions respectively corresponding to the amplifiers, where each of the level measurement portions measures a level of an output signal of a corresponding one of the amplifiers in a level measurement period indicated by a level measurement signal; error calculators respectively corresponding to the level measurement portions, where each of the error calculators compares a level measured by a corresponding one of the level measurement portions with a threshold which is set so that a corresponding one of the amplifiers will not saturate, and outputs a comparison result as an error signal; a gain computation section which updates one of the gains of the amplifiers at a time corresponding to a gain update signal, based on the error signals; and an operation controller which generates the level measurement signal and the gain update signal.
摘要翻译：自动增益控制装置包括级联的放大器，每个具有可变增益; 分别对应于放大器的电平测量部分，其中每个电平测量部分在由电平测量信号指示的电平测量周期中测量相应的一个放大器的输出信号的电平; 分别对应于电平测量部分的误差计算器，其中每个误差计算器将由相应的电平测量部分测量的电平与设置为使得相应的一个放大器不会饱和的阈值进行比较，并输出比较结果作为误差信号; 增益计算部，其基于所述误差信号，在与增益更新信号对应的时刻更新所述放大器的增益中的一者; 以及产生电平测量信号和增益更新信号的操作控制器。

4. 发明授权

US06917317B2 Signal processing device, signal processing method, delta-sigma modulation type fractional division PLL frequency synthesizer, radio communication device, delta-sigma modulation type D/A converter 失效
$Signal processing device, signal processing method, delta-sigma modulation type fractional division PLL frequency synthesizer, radio communication device, delta-sigma modulation type D/A converter$
标题翻译：信号处理装置，信号处理方法，Δ-Σ调制型小数分频PLL频率合成器，无线电通信装置，Δ-Σ调制型D / A转换器
公开(公告)号：US06917317B2
公开(公告)日：2005-07-12
申请号：US10495863
申请日：2003-08-27
申请人： Yoichi Nagaso , Takaharu Saeki
发明人： Yoichi Nagaso , Takaharu Saeki
IPC分类号： H03M1/20 , H03L7/183 , H03L7/197 , H03M1/08 , H03M3/00 , H03M3/02 , H03M7/00 , H03M7/36 , H04B14/06
CPC分类号： H03M7/3008 , H03L7/1978 , H03M7/3042
摘要： A fractional frequency divider (28) includes a latch (31) for holding frequency division data, a ΔΣ modulator (33), a digital dither circuit (32) for receiving a digital input F representing fraction part of the frequency division data from the latch (31) and supplying a digital output alternately changing between F+k and F−k (where k is an integer) or a F value itself to the ΔΣ modulator (33), and circuit means (34 through 38) for executing fractional frequency division based on integer part (M value) of the frequency division data and an output of the ΔΣ modulator (33). The digital dither circuit (32) is useful for suppressing a spurious signal generated as a result of concentration of quantization noise at a particular frequency when the ΔΣ modulator (33) receives a particular F value (e.g., F=2n−1).
摘要翻译：分数分频器（28）包括用于保持分频数据的锁存器（31），DeltaSigma调制器（33），数字抖动电路（32），用于从锁存器接收代表分频数据的分数部分的数字输入F （31），并且向Delta-Σ调制器（33）提供在F + k和Fk（其中k是整数）或F值本身之间交替变化的数字输出，以及用于执行基于分数分频的电路装置（34至38）分频数据的整数部分（M值）和Delta-Σ调制器（33）的输出。数字抖动电路（32）可用于抑制当DeltaSigma调制器（33）接收到特定的F值（例如，F = 2-N）时由于特定频率的量化噪声的集中而产生的寄生信号 1 ）。

5. 发明申请

US20060068697A1 Transmitter 失效
标题翻译：发射机
公开(公告)号：US20060068697A1
公开(公告)日：2006-03-30
申请号：US10522741
申请日：2003-10-23
申请人： Mitsuru Tanabe , Takaharu Saeki , Yoshihisa Minami , Koichiro Tanaka , Noriaki Saito
发明人： Mitsuru Tanabe , Takaharu Saeki , Yoshihisa Minami , Koichiro Tanaka , Noriaki Saito
IPC分类号： H04K3/00
CPC分类号： H03F1/025 , H03F1/02 , H03F1/0244 , H03F3/24 , H03F2200/507 , H03F2200/511 , H04B2001/045
摘要： The present invention provides a transmitter conforming to the EER method in a wide frequency band at high efficiency. For this purpose, the amplitude component of a modulated signal is input to the power supply terminal of a high-frequency power amplifier 130, the I and Q quadrature signals thereof are input to the high-frequency input terminal of the high-frequency power amplifier 130, and the original modulated signal is obtained from the output of the high-frequency power amplifier 130. A collector voltage is supplied from DC-DC converter group 615 having output voltages being different sequentially to an emitter follower 729 via a switch group 621. One of the outputs of the DC-DC converters 616 to 620 is selected depending on the level of the amplitude component as the collector voltage and supplied to the emitter follower, whereby the difference between the emitter voltage of he emitter follower 729 and the collector voltage of the emitter follower 729 is made smaller and the efficiency of the emitter follower 729 is raised; furthermore, the power supply voltage of the high-frequency power amplifier 130 is voltage-converted by the emitter follower 729, whereby operation in a wide frequency band is made possible.
摘要翻译：本发明提供了一种符合EER方法的发射机，在宽频带内具有高效率。为此，调制信号的幅度分量被输入到高频功率放大器130的电源端子，其I和Q正交信号被输入到高频功率放大器的高频输入端 130，并且从高频功率放大器130的输出获得原始调制信号。从具有输出电压的DC-DC转换器组615经由开关组621向发射极跟随器729提供集电极电压。 DC-DC转换器616至620的输出之一根据作为集电极电压的振幅分量的电平来选择，并提供给射极跟随器，由此发射极跟随器729的发射极电压与集电极电压使发射极跟随器729的功率越小，发射极跟随器729的效率越高; 此外，高频功率放大器130的电源电压由射极跟随器729进行电压转换，从而可以在宽频带中进行操作。

6. 发明申请

US20120071127A1 AUTOMATIC GAIN CONTROL DEVICE, RECEIVER, ELECTRONIC DEVICE, AND AUTOMATIC GAIN CONTROL METHOD 审中-公开
标题翻译：自动增益控制装置，接收器，电子装置和自动增益控制方法
公开(公告)号：US20120071127A1
公开(公告)日：2012-03-22
申请号：US13305111
申请日：2011-11-28
申请人： Satoshi TSUKAMOTO , Eiji Okada , Yasuo Oba , Takaharu Saeki
发明人： Satoshi TSUKAMOTO , Eiji Okada , Yasuo Oba , Takaharu Saeki
IPC分类号： H04W52/52
CPC分类号： H03G3/3052
摘要： An automatic gain control device includes an amplifier which amplifies an input signal based on a gain control signal, and outputs an amplified signal, a converter which converts the amplified signal into a converted signal having a value corresponding to an absolute value of the amplified signal, a peak detector which removes, during a peak detection period, from values of the converted signal, a predetermined number of values which include a maximum value, and determines a peak level of the converted signal after the removing, an error calculator which calculates an error between the peak level and a reference signal, and outputs the error as an error signal, and a gain controller which updates the gain control signal based on the error signal, and outputs an updated gain control signal.
摘要翻译：一种自动增益控制装置，包括：放大器，其基于增益控制信号放大输入信号，并输出放大信号;转换器，其将放大信号转换成具有与放大信号的绝对值对应的值的转换信号; 峰值检测器，其在峰值检测周期期间从转换的信号的值，包括最大值的预定数量的值中去除，并且确定去除之后的转换信号的峰值电平，计算误差的误差计算器在峰值电平和参考信号之间，并将误差作为误差信号输出，以及增益控制器，其基于误差信号更新增益控制信号，并输出更新的增益控制信号。

7. 发明申请

US20070103239A1 Delta-sigma type fraction pll synthesizer 审中-公开
$Delta-sigma type fraction pll synthesizer$
标题翻译： Delta-sigma型分数pll合成器
公开(公告)号：US20070103239A1
公开(公告)日：2007-05-10
申请号：US10581262
申请日：2004-12-09
申请人： Takaharu Saeki , Masakatsu Maeda
发明人： Takaharu Saeki , Masakatsu Maeda
IPC分类号： H03L7/00
CPC分类号： H03L7/1976
摘要： An object is to achieve reduction of a spurious in a delta-sigma type fraction division PLL synthesizer. In its configuration, first and second L-value accumulators 31 and 30 are provided. The difference between overflow signals 16 and 17 of the first and the second L-value accumulators 31 and 30 is acquired by an adder 29, so that in response to an output signal of the adder 29, a division ratio of a variable divider 2 having a division ratio switchable between M, M+1, and M−1 is switched. By virtue of this, the frequency of a spurious generated by operation noise of the first and the second L-value accumulators 31 and 30 is shifted to a frequency component higher than the prior art so that the spurious is removed by a loop filter (low pass filter) 5.
摘要翻译：目的是实现在delta-sigma型分数分频PLL合成器中减少杂散。在其结构中，设置有第一和第二L值累加器31和30。通过加法器29获取第一和第二L值累加器31和30的溢出信号16和17之间的差异，使得响应于加法器29的输出信号，具有在M，M + 1和M-1之间切换的分频比被切换。由此，由第一和第二L值累加器31和30的操作噪声产生的杂散频率偏移到比现有技术高的频率分量，使得杂散被环路滤波器（低通过滤波器）5。

8. 发明授权

US07116946B2 Transmitter 失效
标题翻译：发射机
公开(公告)号：US07116946B2
公开(公告)日：2006-10-03
申请号：US10522741
申请日：2003-10-23
申请人： Mitsuru Tanabe , Takaharu Saeki , Yoshihisa Minami , Koichiro Tanaka , Noriaki Saito
发明人： Mitsuru Tanabe , Takaharu Saeki , Yoshihisa Minami , Koichiro Tanaka , Noriaki Saito
IPC分类号： H04B1/02 , H04B1/04 , H01Q11/12
CPC分类号： H03F1/025 , H03F1/02 , H03F1/0244 , H03F3/24 , H03F2200/507 , H03F2200/511 , H04B2001/045
摘要： The present invention provides a transmitter conforming to the EER method in a wide frequency band at high efficiency. For this purpose, the amplitude component of a modulated signal is input to the power supply terminal of a high-frequency power amplifier 130, the I and Q quadrature signals thereof are input to the high-frequency input terminal of the high-frequency power amplifier 130, and the original modulated signal is obtained from the output of the high-frequency power amplifier 130. A collector voltage is supplied from DC—DC converter group 615 having output voltages being different sequentially to an emitter follower 729 via a switch group 621. One of the outputs of the DC—DC converters 616 to 620 is selected depending on the level of the amplitude component as the collector voltage and supplied to the emitter follower, whereby the difference between the emitter voltage of he emitter follower 729 and the collector voltage of the emitter follower 729 is made smaller and the efficiency of the emitter follower 729 is raised; furthermore, the power supply voltage of the high-frequency power amplifier 130 is voltage-converted by the emitter follower 729, whereby operation in a wide frequency band is made possible.
摘要翻译：本发明提供了一种符合EER方法的发射机，在宽频带内具有高效率。为此，调制信号的幅度分量被输入到高频功率放大器130的电源端子，其I和Q正交信号被输入到高频功率放大器的高频输入端 130，并且从高频功率放大器130的输出获得原始调制信号。从具有输出电压的DC-DC转换器组615经由开关组621向发射极跟随器729提供集电极电压。 DC-DC转换器616至620的输出之一根据作为集电极电压的振幅分量的电平来选择，并提供给射极跟随器，由此发射极跟随器729的发射极电压与集电极电压使发射极跟随器729的功率越小，发射极跟随器729的效率越高; 此外，高频功率放大器130的电源电压由射极跟随器729进行电压转换，从而可以在宽频带中进行操作。

9. 发明申请

US20050017887A1 Signal processing device, signal processing method, delta-sigma modulation type fractional division pll frequency synthesizer, radio communication device, delta-sigma modulation type d/a converter 失效
$Signal processing device, signal processing method, delta-sigma modulation type fractional division pll frequency synthesizer, radio communication device, delta-sigma modulation type d/a converter$
标题翻译：信号处理装置，信号处理方法，Δ-Σ调制方式小数分频器频率合成器，无线电通信装置，Δ-Σ调制型d / a转换器
公开(公告)号：US20050017887A1
公开(公告)日：2005-01-27
申请号：US10495863
申请日：2003-08-27
申请人： Yoichi Nagaso , Takaharu Saeki
发明人： Yoichi Nagaso , Takaharu Saeki
IPC分类号： H03M1/20 , H03L7/183 , H03L7/197 , H03M1/08 , H03M3/00 , H03M3/02 , H03M7/00 , H03M7/36 , H04B14/06
CPC分类号： H03M7/3008 , H03L7/1978 , H03M7/3042
摘要： A fractional frequency divider (28) includes a latch (31) for holding frequency division data, a ΔΣ modulator (33), a digital dither circuit (32) for receiving a digital input F representing fraction part of the frequency division data from the latch (31) and supplying a digital output alternately changing between F+k and F−k (where k is an integer) or a F value itself to the ΔΣ modulator (33), and circuit means (34 through 38) for executing fractional frequency division based on integer part (M value) of the frequency division data and an output of the ΔΣ modulator (33). The digital dither circuit (32) is useful for suppressing a spurious signal generated as a result of concentration of quantization noise at a particular frequency when the ΔΣ modulator (33) receives a particular F value (e.g., F=2n−1).
摘要翻译：分数分频器（28）包括用于保持分频数据的锁存器（31），DeltaSigma调制器（33），数字抖动电路（32），用于从锁存器接收代表分频数据的分数部分的数字输入F （31），并且向Delta-Σ调制器（33）提供在F + k和Fk（其中k是整数）或F值本身之间交替变化的数字输出，以及用于执行基于分数分频的电路装置（34至38）分频数据的整数部分（M值）和Delta-Σ调制器（33）的输出。数字抖动电路（32）可用于抑制当DeltaSigma调制器（33）接收到特定的F值（例如，F = 2 ）时由于特定频率处的量化噪声的集中而产生的寄生信号）。

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