专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4780686A Semiconductor differential amplifier 失效
标题翻译：半导体差分放大器
公开(公告)号：US4780686A
公开(公告)日：1988-10-25
申请号：US1028
申请日：1987-01-07
申请人： Shuji Murakami , Katsuki Ichinose
发明人： Shuji Murakami , Katsuki Ichinose
IPC分类号： H03F3/345 , H03F3/45 , H03K19/0952
CPC分类号： H03F3/45076 , H03F2203/45112
摘要： A semiconductor differential amplifier includes first and second MOS transistors of a first conductivity type acting as driver transistors, and third through sixth MOS transistors of a second conductivity type acting as load transistors. First and second input terminals are respectively connected to gate terminals of the first and fifth, and second and sixth transistors. Therefore, since input signals are applied to transistors of both the load and driver sections of the amplifier, the amplifier exhibits a higher sensitivity for detecting relatively small differences between the voltage at the first input terminal and the voltage at the second input terminal.
摘要翻译：半导体差分放大器包括用作驱动晶体管的第一导电类型的第一和第二MOS晶体管，以及用作负载晶体管的第二导电类型的第三至第六MOS晶体管。第一和第二输入端子分别连接到第一和第五和第二和第六晶体管的栅极端子。因此，由于输入信号被施加到放大器的负载和驱动器部分的晶体管，所以放大器具有较高的灵敏度，用于检测第一输入端子处的电压与第二输入端子处的电压之间的较小的差异。

2. 发明授权

US4879690A Static random access memory with reduced soft error rate 失效
标题翻译：具有降低软错误率的静态随机存取存储器
公开(公告)号：US4879690A
公开(公告)日：1989-11-07
申请号：US231063
申请日：1988-08-11
申请人： Kenji Anami , Katsuki Ichinose , Tomohisa Wada
发明人： Kenji Anami , Katsuki Ichinose , Tomohisa Wada
IPC分类号： G11C5/00 , G11C11/412
CPC分类号： G11C11/4125 , G11C5/005
摘要： A storage node in each of memory cells in a static RAM is connected to a bit line through an accessing MOSFET. The accessing MOSFET has its gate connected to a word line. A word line driver comprising a level shifting N channel MOSFET and a CMOS inverter is connected to the word line. At the time of selecting the word line, a potential which is lower, by a threshold voltage of the MOSFET, than a power-supply potential is applied to the word line. Thus, a sub-threshold current flowing in the MOSFET connected between the storage node for storing data at a high level and the bit line to which data of a high level is read out becomes substantially small, so that a potential of the storage node for storing data of a high level is not lowered.
摘要翻译：静态RAM中每个存储单元中的存储节点通过访问MOSFET连接到位线。存取MOSFET的栅极连接到字线。包括电平移位N沟道MOSFET和CMOS反相器的字线驱动器连接到字线。在选择字线时，对字线施加低于MOSFET的阈值电压的电位低于电源电位的电位。因此，在连接在用于存储高电平的数据的存储节点和读出高电平的数据的位线之间的MOSFET中流动的子阈值电流变得基本上小，从而存储节点的电位存储高电平的数据不降低。

3. 发明授权

US5307307A Semiconductor memory device having improved bit line arrangement 失效
标题翻译：具有改进的位线布置的半导体存储器件
公开(公告)号：US5307307A
公开(公告)日：1994-04-26
申请号：US495037
申请日：1990-03-16
申请人： Tomohisa Wada , Katsuki Ichinose
发明人： Tomohisa Wada , Katsuki Ichinose
IPC分类号： G11C11/401 , G11C7/12 , G11C7/18 , G11C11/41 , G11C13/00 , G11C11/00
CPC分类号： G11C7/12 , G11C7/18
摘要： A semiconductor memory device includes a memory cell array composed of a plurality of memory cells. The memory cell array includes a plurality of word lines interconnecting the memory cells in the row direction and a plurality of bit line pairs interconnecting the memory cells in the column direction. One end of each bit line pair is connected to a clamping circuit, while the other end of each bit line pair is connected via a column select gate to a read/write circuit. Each bit line pair is bent about centrally in the two-dimensional form of a letter U and the clamping circuit and the column select gate are disposed alternately on one same straight line.
摘要翻译：半导体存储器件包括由多个存储单元组成的存储单元阵列。存储单元阵列包括将行方向上的存储单元互连的多个字线和在列方向上互连存储单元的多个位线对。每个位线对的一端连接到钳位电路，而每个位线对的另一端通过列选择栅极连接到读/写电路。每个位线对以字母U的二维形式围绕中心弯曲，钳位电路和列选择栅极交替地设置在同一条直线上。

4. 发明授权

US4831590A Semiconductor memory including an output latch having hysteresis characteristics 失效
标题翻译：半导体存储器包括具有滞后特性的输出锁存器
公开(公告)号：US4831590A
公开(公告)日：1989-05-16
申请号：US4584
申请日：1987-01-20
申请人： Katsuki Ichinose
发明人： Katsuki Ichinose
IPC分类号： G11C11/41 , G11C7/10 , G11C11/417 , H03K5/1254 , H03K19/003
CPC分类号： H03K19/00361 , G11C7/1048 , H03K5/1254
摘要： A semiconductor memory device in which an output data bus (14) is precharged at a middle potential level prior to reading out data. A Schmidt Trigger circuit (39) having a hysteresis loop in input-output characteristics is provided between the output data bus (14) and a data output buffer (15). This allows the data output buffer (15) to maintain a stable output (16) while precharging the data bus (14).
摘要翻译：一种半导体存储器件，其中输出数据总线（14）在读出数据之前被预充电为中间电位电平。在输出数据总线（14）和数据输出缓冲器（15）之间提供具有输入 - 输出特性的滞后回路的施密特触发电路（39）。这允许数据输出缓冲器（15）在对数据总线（14）进行预充电的同时保持稳定的输出（16）。

5. 发明授权

US5225705A Semiconductor stress sensor MESFET or MESFET array 失效
标题翻译：半导体应力传感器MESFET或MESFET阵列
公开(公告)号：US5225705A
公开(公告)日：1993-07-06
申请号：US862306
申请日：1992-04-02
申请人： Satoshi Hiyama , Katuhiko Takebe , Katsuki Ichinose
发明人： Satoshi Hiyama , Katuhiko Takebe , Katsuki Ichinose
IPC分类号： G01L9/00 , G01L1/18 , G01L9/04 , G01P15/08 , G01P15/12 , H01L27/20 , H01L29/84
CPC分类号： H01L27/20 , G01P15/124
摘要： A semiconductor sensor has a plurality of field-effect transistors disposed on a semiconductor substrate at spaced intervals. The field-effect transistors have respective drains electrically connected parallel to each other, respective sources electrically connected parallel to each other, and gates electrically connected parallel to each other. While a gate bias voltage is being applied to each of the field-effect transistors, a stress applied to the semiconductor substrate is detected based on a change in a combined output of the field-effect transistors. A single comb-shaped field-effect transistor may be employed instead of the plurality of field effect transistors.

6. 发明授权

US4709354A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4709354A
公开(公告)日：1987-11-24
申请号：US788228
申请日：1985-10-16
申请人： Katsuki Ichinose , Hirofumi Shinohara
发明人： Katsuki Ichinose , Hirofumi Shinohara
IPC分类号： G11C7/00 , G11C8/08 , G11C11/40
CPC分类号： G11C8/08
摘要： A semiconductor memory device includes a plurality of memory cell rows each including a plurality of memory cells; a plurality of row selection signal lines each for transmitting a row selection signal to the memory cells of each memory cell row; and a row decoder for giving a row selection signal to the row selection signal line connected to the memory cells on a memory cell row in accordance with the row address input externally, wherein the row selection signal is at a power supply voltage level during a reading-out period, an intermediate voltage level between the power supply voltage and a ground level during the writing-in period, and the ground level at periods other than the writing-in and reading-out periods.
摘要翻译：半导体存储器件包括多个存储单元行，每个存储单元行包括多个存储单元; 多个行选择信号线，用于将行选择信号发送到每个存储单元行的存储单元; 以及行解码器，用于根据从外部输入的行地址向连接到存储单元行上的存储单元的行选择信号线提供行选择信号，其中行选择信号在读取期间处于电源电压电平在写入期间，电源电压和地电平之间的中间电压电平以及写入和读出周期以外的周期的地电平。

7. 发明授权

US5883739A Information display device for vehicle 失效
标题翻译：汽车信息显示装置
公开(公告)号：US5883739A
公开(公告)日：1999-03-16
申请号：US650590
申请日：1996-05-20
申请人： Jun Ashihara , Katsuki Ichinose , Tsuyoshi Hano , Katsuhiko Takebe
发明人： Jun Ashihara , Katsuki Ichinose , Tsuyoshi Hano , Katsuhiko Takebe
IPC分类号： G02B27/00 , G02B27/01 , G02B27/22 , H04N7/18 , H04N13/00 , H04N13/04 , H04N7/00
CPC分类号： H04N13/0275 , G02B27/01 , G02B27/2214 , H04N13/004 , H04N13/0239 , H04N13/0404 , H04N13/0409 , H04N13/0445 , H04N13/0456 , H04N13/0459 , H04N13/0497 , H04N7/181 , G02B2027/0138 , G02B2027/014 , H04N13/0018 , H04N13/0055 , H04N13/0285 , H04N13/0296 , H04N13/0422 , H04N2013/0081
摘要： An on-board vehicle display arrangement of a computer graphics device and two video cameras for generating left-viewpoint image and right-viewpoint image of vehicle guiding information, an image synthesizer for synthesizing the left-viewpoint image and right-viewpoint image by alternately arranging their elements by pixel, and a stereoscopic display for separately displaying a left-viewpoint image and a right-viewpoint image of the synthesized image, which images are provided inside the vehicle to display a stereoscopic image with outside information taken through the video cameras, vehicle travel guiding information generated by the computer graphics device according to navigation data, presumed travelling information generated by the computer graphics device according to a prospective running condition estimated from the results of detection of current driving conditions of the vehicle.
摘要翻译：一种用于产生车辆引导信息的左视点图像和右视点图像的计算机图形装置和两个摄像机的车载显示装置，用于通过交替布置来合成左视点图像和右视点图像的图像合成器它们的像素单元和用于分别显示合成图像的左视点图像和右视点图像的立体显示器，哪些图像被提供在车辆内部以显示具有通过摄像机拍摄的外部信息的立体图像，车辆由计算机图形装置根据导航数据生成的旅行指导信息，根据从车辆的当前驾驶状况的检测结果估计出的预期运行状况，计算机图形装置生成的推定行驶信息。

8. 发明授权

US5381696A Semiconductor stress sensor 失效
标题翻译：半导体应力传感器
公开(公告)号：US5381696A
公开(公告)日：1995-01-17
申请号：US883752
申请日：1992-05-15
申请人： Katsuki Ichinose , Katuhiko Takebe
发明人： Katsuki Ichinose , Katuhiko Takebe
IPC分类号： G01D3/00 , G01D5/18 , G01L1/18 , G01L9/00 , G01L9/04 , G01P15/12 , H01L29/84 , G01B7/16
CPC分类号： G01P15/124 , G01D5/18 , G01L1/18
摘要： A semiconductor stress sensor includes a field-effect transistor for producing a drain current commensurate with a stress applied thereto. The gate of the field-effect transistor is supplied with a gate bias voltage from a gate bias voltage generator. The drain current from the field-effect transistor is converted into a detected output signal by a current-to-voltage converter. The gate-to-source voltage of the field-effect transistor can be varied to reduce the drain current in a standby mode when no stress is to be detected. To vary the gate-to-source voltage, the gate bias voltage applied to the gate of the field-effect transistor may be slightly varied or the source potential thereof may be slightly varied. The gate-to-source voltage of the field-effect transistor slightly differ from each other in the standby and stress sensing modes. Even in the standby mode, the field-effect transistor is supplied with substantially the same voltage as in the stress sensing mode. When the semiconductor stress sensor switches from the standby mode to the stress sensing mode, the drain current is subjected to an only small drift, allowing the semiconductor stress sensor to produce a highly accurate, stable detected output signal within a short period of time.
摘要翻译：半导体应力传感器包括用于产生与施加到其上的应力相当的漏极电流的场效应晶体管。场效应晶体管的栅极被提供来自栅极偏置电压发生器的栅极偏置电压。来自场效应晶体管的漏极电流由电流 - 电压转换器转换成检测的输出信号。当不需要检测到应力时，可以改变场效应晶体管的栅极 - 源极电压，以便在待机模式下减小漏极电流。为了改变栅极至源极电压，施加到场效应晶体管的栅极的栅极偏置电压可以稍微变化，或者其源极电位可能稍微变化。在待机和应力感测模式下，场效应晶体管的栅源电压略有不同。即使在待机模式下，场效应晶体管被提供与应力感测模式基本上相同的电压。当半导体应力传感器从待机模式切换到应力感测模式时，漏极电流仅经受一个小的漂移，允许半导体应力传感器在短时间内产生高精度，稳定的检测输出信号。

9. 发明授权

US4977538A Semiconductor memory device having hierarchical row selecting lines 失效
标题翻译：具有分级行选择线的半导体存储器件
公开(公告)号：US4977538A
公开(公告)日：1990-12-11
申请号：US400223
申请日：1989-08-29
申请人： Kenji Anami , Katsuki Ichinose
发明人： Kenji Anami , Katsuki Ichinose
IPC分类号： G11C11/401 , G11C7/00 , G11C8/12 , G11C8/14 , G11C11/407 , G11C11/41
CPC分类号： G11C8/14 , G11C8/12
摘要： A memory cell array of this semiconductor memory device is divided into a plurality of large memory cell groups, and each of the large memory cell groups is further divided into a plurality of small memory cell groups. A plurality of main row-selecting lines, a plurality of sub row-selecting lines and a plurality of word lines are provided in the memory cell array, each of the large memory cell groups and each of the small memory cell groups, respectively. Main global decoders select one of the main row-selecting lines in response to an internal address signal. Sub global decoders select a sub row-selecting line associated with the selected main row-selecting line in the large memory cell group selected by a large memory cell group selecting signal. Local decoders select a word line associated with the selected sub row-selecting line in the small memory cell group selected by a small memory cell group selecting signal.
摘要翻译：该半导体存储器件的存储单元阵列被分成多个大存储单元组，并且每个大存储单元组进一步分成多个小存储单元组。多个主行选择线，多个子行选择线和多个字线分别设置在存储单元阵列中，每个大存储单元组和每个小存储单元组。主要全局解码器响应内部地址信号选择主行选择行之一。子全局解码器选择与由大存储器单元组选择信号选择的大存储单元组中的所选主行选择线相关联的子行选择线。本地解码器选择与由小存储单元组选择信号选择的小存储单元组中的所选子行选择线相关联的字线。

10. 发明授权

US5397911A Semiconductor sensor with plural gate electrodes 失效
标题翻译：具有多个栅电极的半导体传感器
公开(公告)号：US5397911A
公开(公告)日：1995-03-14
申请号：US86540
申请日：1993-07-01
申请人： Satoshi Hiyama , Katuhiko Takebe , Katsuki Ichinose
发明人： Satoshi Hiyama , Katuhiko Takebe , Katsuki Ichinose
IPC分类号： G01P15/12 , H01L27/20 , H01L29/84
CPC分类号： G01P15/124 , H01L27/20
摘要： A semiconductor sensor has a plurality of field-effect transistors disposed on a semiconductor substrate at spaced intervals. The field-effect transistors have respective drains electrically connected parallel to each other, respective sources electrically connected parallel to each other, and gates electrically connected parallel to each other. While a gate bias voltage is being applied to each of the field-effect transistors, a stress applied to the semiconductor substrate is detected based on a change in a combined output of the field-effect transistors. A single comb-shaped field-effect transistor or a single planar type field-effect transistor may be employed instead of the plurality of field-effect transistors.
摘要翻译：半导体传感器具有以间隔的间隔设置在半导体衬底上的多个场效应晶体管。场效应晶体管具有彼此并联电连接的各自的漏极，彼此电连接的相应源和彼此并联电连接的栅极。当栅极偏置电压被施加到每个场效应晶体管时，基于场效应晶体管的组合输出的变化来检测施加到半导体衬底的应力。可以使用单个梳状场效应晶体管或单平面型场效应晶体管来代替多个场效应晶体管。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式