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    • 9. 发明授权
    • System for prioritizing slave input register to receive data
transmission via bi-directional data line from master
    • 用于优先从属输入寄存器的系统,用于通过双向数据线从主机接收数据传输
    • US5938746A
    • 1999-08-17
    • US805682
    • 1997-02-25
    • Toshiyuki OzawaShuji MotegiTetsuya Tokunaga
    • Toshiyuki OzawaShuji MotegiTetsuya Tokunaga
    • G06F13/38G06F13/42G06F13/18
    • G06F13/423
    • A master (1) and a slave (3) are connected via a transmission line (5) for sending a clock CL; another transmission line (6) for bidirectionally sending data DT; and still another transmission line (7) for sending a control signal CE. Having turned a control signal CE into "L," the master (1) transmits an address code as data DT to the slave (3). Referring to the content of the transmitted address code, the slave (3) detects whether it is a data transmission from the master (1) to the slave (3) or vice versa. While a control signal CE remains "H," data transmission takes place. Data output from the slave (3) to the data line (6) is managed by a bus driver (22). The bus driver (22) is turned off during a period from when the clock CL became "H" to when a control signal CE becomes "L" after data transmission so that data transmission from the master (1) will not be adversely affected.
    • 主机(1)和从机(3)经由用于发送时钟CL的传输线(5)连接; 用于双向发送数据DT的另一传输线(6); 以及用于发送控制信号CE的又一传输线(7)。 将控制信号CE转换为“L”后,主机(1)将地址码作为数据DT发送到从机(3)。 参照发送的地址码的内容,从机(3)检测是否是从主机(1)到从机(3)的数据传输,反之亦然。 当控制信号CE保持“H”时,发生数据传输。 从总线驱动器(22)管理从从机(3)到数据线(6)的数据输出。 在从时钟CL变为“H”到数据传输之后的控制信号CE变为“L”的期间,总线驱动器(22)被关闭,从而不会对来自主机(1)的数据传输产生不利影响。
    • 10. 发明申请
    • Interface Circuit and a Clock Output Method Therefor
    • 接口电路及其时钟输出方法
    • US20070241797A1
    • 2007-10-18
    • US11736913
    • 2007-04-18
    • Tetsuya TokunagaHiroyuki AraiShuji MotegiTakeshi Hibino
    • Tetsuya TokunagaHiroyuki AraiShuji MotegiTakeshi Hibino
    • H03L7/00
    • G06F1/04
    • An interface circuit outputting a clock signal and data to a data register configured to serially read in the data synchronously with the clock signal, in response to a change of a control signal for outputting the clock signal and the data from one logic level to the other logic level, the interface circuit comprising a clock output circuit configured to: detect a logic level of the clock signal when the control signal changes from the one logic level to the other logic level; output the clock signal on an as-is basis to the data register, when detecting one logic level of the clock signal; and output the clock signal after having changed from the other logic level to the one logic level, to the data register, when detecting the other logic level of the clock signal.
    • 一个接口电路,响应于用于输出时钟信号的控制信号和从一个逻辑电平到另一个逻辑电平的数据的变化,输出时钟信号和数据到数据寄存器,配置为与时钟信号同步地串行读取数据 逻辑电平,所述接口电路包括时钟输出电路,所述时钟输出电路被配置为:当所述控制信号从所述一个逻辑电平改变到另一逻辑电平时,检测所述时钟信号的逻辑电平; 当检测到时钟信号的一个逻辑电平时,将时钟信号原样输出到数据寄存器; 并且当检测到时钟信号的另一个逻辑电平时,在从另一个逻辑电平变为一个逻辑电平之后输出时钟信号到数据寄存器。