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    • 5. 发明申请
    • Backlight Device
    • 背光装置
    • US20080285268A1
    • 2008-11-20
    • US11667397
    • 2005-10-24
    • Takashi OkuTakeo AraiYutaka OtaYasuhiro Tagawa
    • Takashi OkuTakeo AraiYutaka OtaYasuhiro Tagawa
    • F21V9/00
    • G02F1/133603G02F1/133608G02F1/133609G02F1/133611
    • Disclosed is a backlight device for illuminating a transmissive color liquid crystal display panel from its backside with white light. The backlight device includes, as a light source, a plural number of principal light emitting diode units 21mn, and a plural number of subsidiary light emitting diode units 21mn, where m and n are natural numbers. Each principal light emitting diode unit is made up by a plural number of light emitting diodes (21) arrayed in a string and emits white light of preset chromaticity. Each subsidiary light emitting diode unit is made up by a plural number of light emitting diodes (21) arrayed in a string and emits white light of chromaticity in the vicinity of the preset chromaticity. The number of the subsidiary light emitting diode units is smaller than that of the principal light emitting diode units. When the principal light emitting diode units and the subsidiary light emitting diode units are arrayed in a two-dimensional matrix, the subsidiary light emitting diode units 21mn are arrayed without being juxtaposed on the same row, and the subsidiary light emitting diode units 21mn, arrayed in a center column of the two-dimensional matrix, are arrayed towards the center of a color liquid crystal display panel (110).
    • 公开了一种背光装置,其用白光从其背面照射透射彩色液晶显示面板。 背光装置包括多个主发光二极管单元21和多个辅助发光二极管单元21,作为光源,其中, m和n是自然数。 每个主要发光二极管单元由排列成串的多个发光二极管(21)构成并发出预定色度的白光。 每个辅助发光二极管单元由排列成串的多个发光二极管(21)构成,并且在预设色度附近发出色度的白光。 辅助发光二极管单元的数量小于主要发光二极管单元的数量。 当主发光二极管单元和辅助发光二极管单元排列成二维矩阵时,辅助发光二极管单元21排列而不并列在同一行上,并且 排列在二维矩阵的中心列中的辅助发光二极管单元21 朝向彩色液晶显示面板(110)的中心排列。
    • 6. 发明授权
    • Backlight device
    • 背光装置
    • US07946723B2
    • 2011-05-24
    • US11667397
    • 2005-10-24
    • Takashi OkuTakeo AraiYutaka OtaYasuhiro Tagawa
    • Takashi OkuTakeo AraiYutaka OtaYasuhiro Tagawa
    • G09F13/04
    • G02F1/133603G02F1/133608G02F1/133609G02F1/133611
    • Disclosed is a backlight device for illuminating a transmissive color liquid crystal display panel from its backside with white light. The backlight device includes, as a light source, a plural number of principal light emitting diode units 21mn, and a plural number of subsidiary light emitting diode units 21mn, where m and n are natural numbers. Each principal light emitting diode unit is made up by a plural number of light emitting diodes (21) arrayed in a string and emits white light of preset chromaticity. Each subsidiary light emitting diode unit is made up by a plural number of light emitting diodes (21) arrayed in a string and emits white light of chromaticity in the vicinity of the preset chromaticity. The number of the subsidiary light emitting diode units is smaller than that of the principal light emitting diode units. When the principal light emitting diode units and the subsidiary light emitting diode units are arrayed in a two-dimensional matrix, the subsidiary light emitting diode units 21mn are arrayed without being juxtaposed on the same row, and the subsidiary light emitting diode units 21mn, arrayed in a center column of the two-dimensional matrix, are arrayed towards the center of a color liquid crystal display panel (110).
    • 公开了一种背光装置,其用白光从其背面照射透射彩色液晶显示面板。 背光装置包括多个主发光二极管单元21mn和多个辅助发光二极管单元21mn作为光源,其中m和n是自然数。 每个主要发光二极管单元由排列成串的多个发光二极管(21)构成并发出预定色度的白光。 每个辅助发光二极管单元由排列成串的多个发光二极管(21)构成,并在预设色度附近发出色度的白光。 辅助发光二极管单元的数量小于主要发光二极管单元的数量。 当主发光二极管单元和辅助发光二极管单元被排列成二维矩阵时,辅助发光二极管单元21mn被排列而不并置在同一行上,并且辅助发光二极管单元21mn排列 在二维矩阵的中心列中朝向彩色液晶显示面板(110)的中心排列。
    • 7. 发明授权
    • LCOS projector having signal correction processing based on projection lens distortion
    • LCOS投影机具有基于投影透镜失真的信号校正处理
    • US08888296B2
    • 2014-11-18
    • US13421540
    • 2012-03-15
    • Yutaka OtaRyuji Hada
    • Yutaka OtaRyuji Hada
    • G03B21/14G09G3/00G06T1/20H04N9/31G09G5/39G06T1/60
    • G03B21/147G06T1/20G06T1/60G09G3/002G09G5/39G09G2340/04H04N9/312H04N9/3179H04N9/3185H04N9/3188
    • A projector is provided with: an input line memory which holds an input image signal corresponding to one line; an image processor which generates an intermediate image signal correction-processed according to distortion of a projection lens, using the input image signal transferred from the input line memory; an output line memory which holds the intermediate image signal corresponding to one line; and an LCOS which guides light radiated from a light source to the projection lens in accordance with the intermediate image signal. The image processor is provided with an input supplementation buffer which stores the input image signals of a plurality of lines, an input data buffer which stores input image signals required to generate the intermediate image signal corresponding to one line, and a number-of-supplementary-lines calculator which calculates the number of supplementary lines of the input image signals.
    • 投影仪具有:保持对应于一行的输入图像信号的输入行存储器; 图像处理器,使用从输入行存储器传送的输入图像信号,生成根据投影透镜的失真进行了校正处理的中间图像信号; 保持对应于一行的中间图像信号的输出行存储器; 以及根据中间图像信号将从光源照射的光引导到投影透镜的LCOS。 图像处理器设置有存储多条线的输入图像信号的输入补充缓冲器,存储生成对应于一行的中间图像信号所需的输入图像信号的输入数据缓冲器,以及补充数量 线计算器,其计算输入图像信号的补充行数。
    • 8. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US08476641B2
    • 2013-07-02
    • US12745133
    • 2008-09-08
    • Yoshiyuki SudaYutaka Ota
    • Yoshiyuki SudaYutaka Ota
    • H01L29/24
    • H01L27/101G11C13/0002G11C2213/72H01L21/8213H01L27/1021H01L27/1022H01L27/24
    • A switching resistance RAM that is highly integrated as well as reduced in a read-out time is realized. There is formed an NPN type bipolar transistor BT composed of a collector layer made of an N-well 11, a base layer made of a P+ type Si layer 12A formed in a surface of the N-well 11, and an emitter layer made of an N+ type Si layer 15 formed in a surface of the P+ type Si layer 12A. Also, there are formed a word line WL0 electrically connected to the N+ type Si layer 15 and bit lines BL1-BL4 intersecting with the word line WL0. Also, there are formed a plurality of switching layers 14 formed on a surface of the P+ type Si layer 12A, each being electrically connected to corresponding each of the bit lines and switching between an ON state and an OFF state and an electric potential fixing line 19A to fix the P+ type Si layer 12A at a predetermined electric potential.
    • 实现高集成度以及减少读出时间的开关电阻RAM。 形成由N阱11构成的集电极构成的NPN型双极晶体管BT,在N阱11的表面形成的由P +型Si层12A构成的基极层和由N阱11的表面形成的发射极层 形成在P +型Si层12A的表面上的N +型Si层15。 而且,形成与N +型Si层15电连接的字线WL0,与字线WL0相交的位线BL1〜BL4。 此外,形成在P +型Si层12A的表面上形成的多个开关层14,其各自与对应的每个位线电连接,并且在导通状态和断开状态之间切换以及电位固定线 19A以将P +型Si层12A固定在预定电位。
    • 9. 发明授权
    • Source code analyzing system and source code analyzing method
    • 源代码分析系统和源代码分析方法
    • US08266596B2
    • 2012-09-11
    • US12713817
    • 2010-02-26
    • Yuji IshikawaYutaka OtaYu Nakanishi
    • Yuji IshikawaYutaka OtaYu Nakanishi
    • G06F9/44
    • G06F8/51
    • Every time an assignment statement is executed during performing a simulation according to a second variable memory system, it is determined whether a value interpreted to have the same meaning is assigned to the assignment statement in the simulation according to a first variable memory system and in the simulation according to the second variable memory system. When the value interpreted to have the same meaning is not assigned, the value assigned according to the second variable memory system is overwritten by an expected value, and a report indicating that the assignment statement is a part dependent on a variable memory system is output.
    • 在根据第二可变存储器系统执行仿真期间每次执行分配语句时,根据第一可变存储器系统确定在模拟中是否将解释为具有相同含义的值分配给模拟中的赋值语句,并且在 根据第二个可变存储器系统进行仿真。 当被解释为具有相同含义的值被分配时,根据第二变量存储器系统分配的值被预期值覆盖,并且输出指示分配语句是依赖于可变存储器系统的部分的报告。
    • 10. 发明申请
    • SEMICONDUCTOR MEMORY DEVICE
    • 半导体存储器件
    • US20100308341A1
    • 2010-12-09
    • US12745133
    • 2008-09-08
    • Yoshiyuki SudaYutaka Ota
    • Yoshiyuki SudaYutaka Ota
    • H01L29/24
    • H01L27/101G11C13/0002G11C2213/72H01L21/8213H01L27/1021H01L27/1022H01L27/24
    • A switching resistance RAM that is highly integrated as well as reduced in a read-out time is realized. There is formed an NPN type bipolar transistor BT composed of a collector layer made of an N-well 11, a base layer made of a P+ type Si layer 12A formed in a surface of the N-well 11, and an emitter layer made of an N+ type Si layer 15 formed in a surface of the P+ type Si layer 12A. Also, there are formed a word line WL0 electrically connected to the N+ type Si layer 15 and bit lines BL1-BL4 intersecting with the word line WL0. Also, there are formed a plurality of switching layers 14 formed on a surface of the P+ type Si layer 12A, each being electrically connected to corresponding each of the bit lines and switching between an ON state and an OFF state and an electric potential fixing line 19A to fix the P+ type Si layer 12A at a predetermined electric potential.
    • 实现高集成度以及减少读出时间的开关电阻RAM。 形成由N阱11构成的集电极构成的NPN型双极晶体管BT,在N阱11的表面形成的由P +型Si层12A构成的基极层和由N阱11的表面形成的发射极层 形成在P +型Si层12A的表面上的N +型Si层15。 而且,形成与N +型Si层15电连接的字线WL0,与字线WL0相交的位线BL1〜BL4。 此外,形成在P +型Si层12A的表面上形成的多个开关层14,其各自与对应的每个位线电连接,并且在导通状态和断开状态之间切换以及电位固定线 19A以将P +型Si层12A固定在预定电位。