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1. 发明授权

US07870350B1 Write buffer for read-write interlocks 有权
标题翻译：用于读写互锁的写缓冲区
公开(公告)号：US07870350B1
公开(公告)日：2011-01-11
申请号：US11759539
申请日：2007-06-07
申请人： Shu-Yi Yu , James Michael O'Connor
发明人： Shu-Yi Yu , James Michael O'Connor
IPC分类号： G06F13/00
CPC分类号： G06F13/161
摘要： A write buffer for read-write interlocks improves memory access performance by minimizing the latency needed to avoid a read-after-write hazard when a read follows a write to the same memory location. Rather than waiting until a write has been stored in the memory location, the write buffer provides an acknowledgement signal before the data has been stored in memory in order for a subsequent read of the memory location to proceed. The write buffer merges the data to be written with any data that is stored in memory for the read request to return the current data for the read request.
摘要翻译：用于读写互锁的写缓冲器通过最小化在读写到同一存储单元时避免读写后危险所需的延迟来提高存储器访问性能。写缓冲器不是等待写入已经存储在存储器位置中，而是在数据已经存储在存储器中之前提供确认信号，以便继续读取存储器位置。写入缓冲区将要写入的数据与存储在读取请求的存储器中的任何数据合并，以返回读取请求的当前数据。

2. 发明授权

US08365015B1 Memory-based error recovery 有权
标题翻译：基于内存的错误恢复
公开(公告)号：US08365015B1
公开(公告)日：2013-01-29
申请号：US12853121
申请日：2010-08-09
申请人： Shu-Yi Yu , Shane Keil , John Edmondson
发明人： Shu-Yi Yu , Shane Keil , John Edmondson
IPC分类号： G06F11/00
CPC分类号： G06F11/1008 , G06F9/3863
摘要： The present disclosure provides memory level error correction methods and apparatus. A memory controller is intermediate the memory devices, such as DRAM chips or memory modules, and a processor, such a graphics processor or a main processor. The memory controller can provide error correction. In an example, the memory controller includes a buffer to store instructions and data for execution by the controller and a replay buffer to store the instructions such that operations can be replayed to prior state before the error. An error detector receives data read from the memory devices and if no error is detected outputs the data. If an error is detected, the error detector signals the memory controller to replay the instructions stored in the replay buffer.
摘要翻译：本公开提供了存储器级错误校正方法和装置。存储器控制器在诸如DRAM芯片或存储器模块的存储器件之间，以及诸如图形处理器或主处理器的处理器之间。存储器控制器可以提供纠错。在一个示例中，存储器控制器包括一个缓冲器，用于存储用于由控制器执行的指令和数据以及重放缓冲器来存储指令，使得可以在错误之前将操作重播到先前的状态。错误检测器接收从存储器件读取的数据，如果没有检测到错误则输出数据。如果检测到错误，则错误检测器通知存储器控制器重放存储在重放缓冲器中的指令。

3. 发明授权

US08924740B2 Encryption key transmission with power analysis attack resistance 有权
标题翻译：加密密钥传输具有功率分析攻击阻力
公开(公告)号：US08924740B2
公开(公告)日：2014-12-30
申请号：US13314420
申请日：2011-12-08
申请人： Shu-Yi Yu
发明人： Shu-Yi Yu
IPC分类号： H04L9/00
CPC分类号： H04L9/003 , G06F21/755 , H04L9/08
摘要： Methods and mechanisms for transmitting secure data. An apparatus includes a storage device configured to store data intended to be kept secure. Circuitry is configured to receive bits of the secure data from the storage device and invert the bits prior to transmission. The circuitry may invert the bits prior to conveyance if more than half of the bits are a binary one, set an inversion signal to indicate whether the one or more bits are inverted, and convey both the one or more bits and inversion signal. Embodiments also include a first source configured to transmit Q bits of the secure data on an interface on each of a plurality of clock cycles. The first source is also configured to generate one or more additional bits to be conveyed concurrent with the Q bits such that a number of binary ones transmitted each clock cycle is constant.
摘要翻译：传输安全数据的方法和机制。一种装置包括被配置为存储旨在保持安全的数据的存储装置。电路被配置为从存储设备接收安全数据的比特并在发送之前反转比特。如果多于一半的位是二进制的，则电路可以在传送之前反转位，设置反相信号以指示一个或多个位是否反相，并且传送一个或多个位和反相信号。实施例还包括被配置为在多个时钟周期中的每个时钟周期上在接口上传送安全数据的Q位的第一源。第一源还被配置为生成与Q位同时传送的一个或多个附加位，使得每个时钟周期传输的二进制数的数量是恒定的。

4. 发明授权

US08812892B1 Hardware WCK2CK training engine using meta-EDC sweeping and adjustably accurate voting algorithm for clock phase detection 有权
标题翻译：硬件WCK2CK培训引擎采用meta-EDC扫描和可调精确的投票算法进行时钟相位检测
公开(公告)号：US08812892B1
公开(公告)日：2014-08-19
申请号：US12650242
申请日：2009-12-30
申请人： Eric Lyell Hill , Russell R. Newcomb , Shu-Yi Yu
发明人： Eric Lyell Hill , Russell R. Newcomb , Shu-Yi Yu
IPC分类号： G06F1/12 , G06F1/10
CPC分类号： G06F1/10
摘要： One embodiment of the present invention sets forth a technique for performing high-performance clock training. One clock training sweep operation is performed to determine phase relationships for two write clocks with respect to a command clock. The phase relationships are generated to satisfy timing requirements for two different client devices, such as GDDR5 DRAM components. A second clock training sweep operation is performed to better align local clocks operating on the client devices. A voting tally is maintained during the second clock training sweep to record phase agreement at each step in the clock training sweep. The voting tally then determines whether one of the local clocks should be inverted to better align the two local clocks.
摘要翻译：本发明的一个实施例提出了一种用于执行高性能时钟训练的技术。执行一个时钟训练扫描操作以确定相对于命令时钟的两个写入时钟的相位关系。生成相位关系以满足两种不同客户端设备（如GDDR5 DRAM组件）的时序要求。执行第二时钟训练扫描操作以更好地对准在客户端设备上操作的本地时钟。在第二次时钟训练扫描期间保持投票记录，以在时钟训练扫描的每个步骤记录相位协议。然后，投票计数确定是否应将本地时钟之一反转以更好地对准两个本地时钟。

5. 发明申请

US20140068204A1 Low Power, Area-Efficient Tracking Buffer 有权
标题翻译：低功耗，高效跟踪缓冲区
公开(公告)号：US20140068204A1
公开(公告)日：2014-03-06
申请号：US13605496
申请日：2012-09-06
申请人： Shu-Yi Yu
发明人： Shu-Yi Yu
IPC分类号： G06F12/08
CPC分类号： G06F13/4027 , Y02D10/14 , Y02D10/151
摘要： A tracking buffer apparatus is disclosed. A tracking buffer apparatus includes lookup logic configured to locate entries having a transaction identifier corresponding to a received request. The lookup logic is configured to determine which of the entries having the same transaction identifier has a highest priority and thus cause a corresponding entry from a data buffer to be provided. When information is written into the tracking buffer, write logic writes a corresponding transaction identifier to the first free entry. The write logic also writes priority information in the entry based on other entries having the same transaction identifier. The entry currently being written may be assigned a lower priority than all other entries having the same transaction identifier. The priority information for entries having a common transaction identifier with one currently being read are updated responsive to the read operation.
摘要翻译：公开了一种跟踪缓冲装置。跟踪缓冲装置包括查找逻辑，其被配置为定位具有对应于接收到的请求的事务标识符的条目。查找逻辑被配置为确定具有相同事务标识符的哪些条目具有最高优先级，并且因此导致提供来自数据缓冲器的相应条目。当信息写入跟踪缓冲器时，写入逻辑将相应的事务标识符写入第一个空闲条目。写入逻辑还基于具有相同事务标识符的其他条目在条目中写入优先级信息。当前正在写入的条目可以被分配给具有相同事务标识符的所有其他条目的优先级较低。响应于读取操作更新具有当前正在读取的公共事务标识符的条目的优先级信息。

6. 发明授权

US08489911B1 Hardware WCK2CK training engine using meta-EDC sweeping and adjustably accurate voting algorithm for clock phase detection 有权
标题翻译：硬件WCK2CK培训引擎采用meta-EDC扫描和可调精确的投票算法进行时钟相位检测
公开(公告)号：US08489911B1
公开(公告)日：2013-07-16
申请号：US12650281
申请日：2009-12-30
申请人： Eric Lyell Hill , Russell R. Newcomb , Shu-Yi Yu
发明人： Eric Lyell Hill , Russell R. Newcomb , Shu-Yi Yu
IPC分类号： G06F1/12 , G06F1/10
CPC分类号： G06F1/10
摘要： One embodiment of the present invention sets forth a technique for performing high-performance clock training. One clock training sweep operation is performed to determine phase relationships for two write clocks with respect to a command clock. The phase relationships are generated to satisfy timing requirements for two different client devices, such as GDDR5 DRAM components. A second clock training sweep operation is performed to better align local clocks operating on the client devices. A voting tally is maintained during the second clock training sweep to record phase agreement at each step in the clock training sweep. The voting tally then determines whether one of the local clocks should be inverted to better align the two local clocks.
摘要翻译：本发明的一个实施例提出了一种用于执行高性能时钟训练的技术。执行一个时钟训练扫描操作以确定相对于命令时钟的两个写入时钟的相位关系。生成相位关系以满足两种不同客户端设备（如GDDR5 DRAM组件）的时序要求。执行第二时钟训练扫描操作以更好地对准在客户端设备上操作的本地时钟。在第二次时钟训练扫描期间保持投票记录，以在时钟训练扫描的每个步骤记录相位协议。然后，投票计数确定是否应将本地时钟之一反转以更好地对准两个本地时钟。

7. 发明申请

US20130151842A1 ENCRYPTION KEY TRANSMISSION WITH POWER ANALYIS ATTACK RESISTANCE 有权
标题翻译：具有功率分析攻击电阻的加密密钥传输
公开(公告)号：US20130151842A1
公开(公告)日：2013-06-13
申请号：US13314420
申请日：2011-12-08
申请人： Shu-Yi Yu
发明人： Shu-Yi Yu
IPC分类号： H04L9/00
CPC分类号： H04L9/003 , G06F21/755 , H04L9/08
摘要： Methods and mechanisms for transmitting secure data. An apparatus includes a storage device configured to store data intended to be kept secure. Circuitry is configured to receive bits of the secure data from the storage device and invert the bits prior to transmission. The circuitry may invert the bits prior to conveyance if more than half of the bits are a binary one, set an inversion signal to indicate whether the one or more bits are inverted, and convey both the one or more bits and inversion signal. Embodiments also include a first source configured to transmit Q bits of the secure data on an interface on each of a plurality of clock cycles. The first source is also configured to generate one or more additional bits to be conveyed concurrent with the Q bits such that a number of binary ones transmitted each clock cycle is constant.
摘要翻译：传输安全数据的方法和机制。一种装置包括被配置为存储旨在保持安全的数据的存储装置。电路被配置为从存储设备接收安全数据的比特并在发送之前反转比特。如果多于一半的位是二进制的，则电路可以在传送之前反转位，设置反相信号以指示一个或多个位是否反相，并且传送一个或多个位和反相信号。实施例还包括被配置为在多个时钟周期中的每个时钟周期上在接口上传送安全数据的Q位的第一源。第一源还被配置为生成与Q位同时传送的一个或多个附加位，使得每个时钟周期传输的二进制数的数量是恒定的。

8. 发明授权

US08370705B1 System and method for calculating a checksum address while maintaining error correction information 有权
标题翻译：用于计算校验和地址同时保持纠错信息的系统和方法
公开(公告)号：US08370705B1
公开(公告)日：2013-02-05
申请号：US12565169
申请日：2009-09-23
申请人： Shu-Yi Yu , Kevin Cameron
发明人： Shu-Yi Yu , Kevin Cameron
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： H03M13/09
摘要： One or more embodiments of the invention set forth techniques to perform integer division using addition operations in order to provide address translation capabilities to a processor. The processor supports a memory that maintains checksum information such that address requests received by the processor need to be translated to a checksum address and an actual data address that accounts for use of portions of the memory to store checksum information. Once the checksum address and the actual data address are computed, the processor can confirm the integrity of the data stored in the actual data address and correct any errors if need be, based on the checksum information stored in the checksum address.
摘要翻译：本发明的一个或多个实施例提出了使用加法运算执行整数除法以便向处理器提供地址转换能力的技术。处理器支持维持校验和信息的存储器，使得由处理器接收的地址请求需要被转换成校验和地址和实际的数据地址，该数据地址用于存储部分存储器以存储校验和信息。一旦计算了校验和地址和实际数据地址，则处理器可以基于存储在校验和地址中的校验和信息来确认存储在实际数据地址中的数据的完整性，并根据需要校正任何错误。

9. 发明授权

US07271810B1 Spread-compensated anisotropic texture sampling 有权
标题翻译：扩展补偿各向异性纹理采样
公开(公告)号：US07271810B1
公开(公告)日：2007-09-18
申请号：US11069666
申请日：2005-03-01
申请人： William P. Newhall, Jr. , Shu-Yi Yu
发明人： William P. Newhall, Jr. , Shu-Yi Yu
IPC分类号： G09G5/00
CPC分类号： G06T15/04 , G09G5/003 , G09G2340/0407
摘要： Systems and methods for determining the number of texture samples used to produce an anisotropically filtered texture mapped pixel may improve texture mapping performance or image quality. The number of texture samples may be increased or decreased based on texture state variables that may be specific to each texture map. Furthermore, the texture samples may be positioned along an axis of anisotropy to approximate an elliptical footprint, ensuring that the texture samples span the entire axis of anisotropy. A graphics driver may load the texture state variables and configure a system to modify the number of texture samples and/or position the texture samples used to produce the anisotropically filtered texture mapped pixel.
摘要翻译：用于确定用于产生各向异性滤波的纹理映射像素的纹理样本数量的系统和方法可以改善纹理映射性能或图像质量。可以基于可以对每个纹理贴图特定的纹理状态变量来增加或减少纹理样本的数量。此外，纹理样本可以沿着各向异性轴定位，以接近椭圆形的足迹，确保纹理样本跨越各向异性的整个轴。图形驱动器可以加载纹理状态变量并且配置系统来修改纹理样本的数量和/或定位用于产生各向异性滤波的纹理映射像素的纹理样本。

10. 发明授权

US09436625B2 Approach for allocating virtual bank managers within a dynamic random access memory (DRAM) controller to physical banks within a DRAM 有权
标题翻译：将动态随机存取存储器（DRAM）控制器内的虚拟存储体管理器分配给DRAM内的物理存储体的方法
公开(公告)号：US09436625B2
公开(公告)日：2016-09-06
申请号：US13517534
申请日：2012-06-13
申请人： Shu-Yi Yu , Ram Gummadi , John H. Edmondson
发明人： Shu-Yi Yu , Ram Gummadi , John H. Edmondson
IPC分类号： G06F12/00 , G06F13/16 , G06F12/06 , G06F12/10 , G06F9/50
CPC分类号： G06F13/1668 , G06F9/5077 , G06F12/0653 , G06F12/10 , G06F2212/1028 , Y02D10/13 , Y02D10/14
摘要： Banks within a dynamic random access memory (DRAM) are managed with virtual bank managers. A DRAM controller receives a new memory access request to DRAM including a plurality of banks. If the request accesses a location in DRAM where no virtual bank manager includes parameters for the corresponding DRAM page, then a virtual bank manager is allocated to the physical bank associated with the DRAM page. The bank manager is initialized to include parameters needed by the DRAM controller to access the DRAM page. The memory access request is then processed using the parameters associated with the virtual bank manager. One advantage of the disclosed technique is that the banks of a DRAM module are controlled with fewer bank managers than in previous DRAM controller designs. As a result, less surface area on the DRAM controller circuit is dedicated to bank managers.
摘要翻译：动态随机存取存储器（DRAM）中的银行由虚拟银行经理管理。 DRAM控制器接收对包括多个存储体的DRAM的新的存储器访问请求。如果请求访问DRAM中没有虚拟存储体管理器包括相应的DRAM页面的参数的位置，则将虚拟存储体管理器分配给与DRAM页面相关联的物理存储体。银行经理被初始化以包括DRAM控制器所需的参数来访问DRAM页面。然后使用与虚拟银行管理器相关联的参数来处理存储器访问请求。所公开的技术的一个优点在于，DRAM模块的组由前面的DRAM控制器设计中的银行管理器来控制。因此，DRAM控制器电路上的较少的表面积专用于银行经理。

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