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1. 发明申请

US20090317915A1 Biochip detection device and detection method therof 审中-公开
标题翻译：生物芯片检测装置及检测方法
公开(公告)号：US20090317915A1
公开(公告)日：2009-12-24
申请号：US12453700
申请日：2009-05-20
申请人： Shu-Jen Han , Joseph Shu-Tzu Han
发明人： Shu-Jen Han , Joseph Shu-Tzu Han
IPC分类号： G01N27/00
CPC分类号： G01R33/093 , B82Y25/00 , G01R33/1269
摘要： The present invention provides a biochip detection device and a detection method thereof. The detection device includes a detection circuit and a biochip containing a plurality of sensor modules. Each sensor modules includes a plurality of giant magnetoresistive biosensors. The detection circuit is arranged to have an end of each biosensor and an end of each of reference sensors respectively connected to first and second voltage sources, whereby current variation induced in each biosensor can be added together. The detection method includes the steps of providing the above described biochip; carrying out surface functionalization on the biosensors; spotting surfaces of the biosensors with probe molecules corresponding to target molecules to complete molecule immobilization; applying a purified sample to the biochip so that target molecules existing in the sample bind to the probe molecules on the surfaces of the biosensors; applying detecting molecules that are combined with magnetic nano-particles to the biochip in such a way that the detecting molecules are complementary to and thus bound to the target molecules; and using the above mentioned detection circuit to supply an output of a detection current of the biosensors so that observation of variation thereof is made to determine existence of the target molecules.
摘要翻译：本发明提供一种生物芯片检测装置及其检测方法。检测装置包括检测电路和包含多个传感器模块的生物芯片。每个传感器模块包括多个巨磁阻生物传感器。检测电路设置成具有每个生物传感器的端部，并且每个参考传感器的端部分别连接到第一和第二电压源，由此可以将每个生物传感器中引起的电流变化加在一起。检测方法包括提供上述生物芯片的步骤; 在生物传感器上进行表面官能化; 用对应于靶分子的探针分子发射生物传感器的表面以完成分子固定化; 将纯化的样品施加到生物芯片上，使得存在于样品中的靶分子与生物传感器表面上的探针分子结合; 将与磁性纳米颗粒结合的检测分子施加到生物芯片上，使得检测分子与靶分子互补并因此结合到靶分子; 并且使用上述检测电路来提供生物传感器的检测电流的输出，使得观察其变化来确定目标分子的存在。

2. 发明授权

US09076873B2 Graphene devices with local dual gates 有权
公开(公告)号：US09076873B2
公开(公告)日：2015-07-07
申请号：US12986342
申请日：2011-01-07
申请人： Zhihong Chen , Aaron Daniel Franklin , Shu-Jen Han
发明人： Zhihong Chen , Aaron Daniel Franklin , Shu-Jen Han
IPC分类号： H01L29/66 , H01L29/786 , H01L29/16 , H01L29/49
CPC分类号： H01L29/66045 , H01L21/02178 , H01L21/02181 , H01L21/02527 , H01L21/044 , H01L29/1606 , H01L29/42376 , H01L29/42384 , H01L29/4908 , H01L29/4916 , H01L29/517 , H01L29/66015 , H01L29/66742 , H01L29/78645 , H01L29/78648 , H01L29/78684
摘要： An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer.

3. 发明授权

US09068936B2 Graphene sensor 有权
公开(公告)号：US09068936B2
公开(公告)日：2015-06-30
申请号：US13605107
申请日：2012-09-06
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
IPC分类号： H01L29/786 , H01L21/336 , G01N27/414 , H01L29/423 , H01L29/49 , H01L29/66
CPC分类号： G01N27/4145 , G01N27/4146 , H01L29/1606 , H01L29/42384 , H01L29/4908 , H01L29/66742 , H01L29/78684 , H01L51/0048
摘要： A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.

4. 发明授权

US08895371B2 Transistor employing vertically stacked self-aligned carbon nanotubes 有权
标题翻译：晶体管采用垂直堆叠的自对准碳纳米管
公开(公告)号：US08895371B2
公开(公告)日：2014-11-25
申请号：US13605238
申请日：2012-09-06
申请人： Qing Cao , Dechao Guo , Shu-Jen Han , Yu Lu , Keith Kwong Hon Wong
发明人： Qing Cao , Dechao Guo , Shu-Jen Han , Yu Lu , Keith Kwong Hon Wong
IPC分类号： H01L21/335 , H01L51/05 , H01L29/775 , H01L29/66 , H01L51/00 , H01L29/12 , B82Y10/00 , B82Y30/00 , H01L29/78
CPC分类号： H01L51/057 , B82Y10/00 , B82Y30/00 , H01L29/125 , H01L29/66439 , H01L29/775 , H01L29/7827 , H01L51/0045 , H01L51/0048 , Y10S977/742 , Y10S977/842 , Y10S977/938
摘要： A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel.
摘要翻译：形成包括具有第一等电点的第一等电点材料层和具有小于第一等电点的第二等电点的第二等电子材料层的垂直交替堆叠的鳍结构。第一和第二等电点材料层在具有第一和第二等电点之间的pH的溶液中相反地充电。通过阴离子表面活性剂将负电荷赋予碳纳米管。静电引力使得碳纳米管选择性地附着在第一等电点材料层的表面上。碳纳米管沿翅片结构的水平长度方向自对准地附接到第一等电点材料层。可以形成晶体管，其采用多个垂直排列的水平碳纳米管作为沟道。

5. 发明授权

US08890116B2 Vertical stacking of carbon nanotube arrays for current enhancement and control 有权
标题翻译：用于当前增强和控制的碳纳米管阵列的垂直堆叠
公开(公告)号：US08890116B2
公开(公告)日：2014-11-18
申请号：US13610089
申请日：2012-09-11
申请人： Zhihong Chen , Aaron Daniel Franklin , Shu-Jen Han
发明人： Zhihong Chen , Aaron Daniel Franklin , Shu-Jen Han
IPC分类号： H01L29/06 , H01L51/00 , B82Y10/00 , H01L51/05
CPC分类号： H01L51/0048 , B82Y10/00 , H01L51/0558 , Y10S977/742 , Y10S977/938
摘要： Transistor devices having vertically stacked carbon nanotube channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; a bottom gate embedded in the substrate with a top surface of the bottom gate being substantially coplanar with a surface of the substrate; a stack of device layers on the substrate over the bottom gate, wherein each of the device layers in the stack includes a first dielectric, a carbon nanotube channel on the first dielectric, a second dielectric on the carbon nanotube channel and a top gate on the second dielectric; and source and drain contacts that interconnect the carbon nanotube channels in parallel. A method of fabricating a transistor device is also provided.
摘要翻译：提供具有垂直堆叠的碳纳米管通道的晶体管器件及其制造技术。一方面，提供一种晶体管器件。晶体管器件包括衬底; 嵌入基板中的底栅与底栅的顶表面基本上与基板的表面共面; 在底栅上的衬底上的一叠器件层，其中堆叠中的每个器件层包括第一电介质，第一电介质上的碳纳米管通道，碳纳米管通道上的第二电介质和第二电介质; 以及并联连接碳纳米管通道的源极和漏极触点。还提供了一种制造晶体管器件的方法。

6. 发明授权

US08785911B2 Graphene or carbon nanotube devices with localized bottom gates and gate dielectric 有权
标题翻译：具有局部底栅和栅极电介质的石墨烯或碳纳米管器件
公开(公告)号：US08785911B2
公开(公告)日：2014-07-22
申请号：US13167570
申请日：2011-06-23
申请人： Zhihong Chen , Aaron Daniel Franklin , Shu-Jen Han , James Bowler Hannon , Katherine L. Saenger , George Stojan Tulevski
发明人： Zhihong Chen , Aaron Daniel Franklin , Shu-Jen Han , James Bowler Hannon , Katherine L. Saenger , George Stojan Tulevski
IPC分类号： H01L21/336
CPC分类号： H01L29/7781 , B82Y10/00 , B82Y30/00 , H01L29/1075 , H01L29/1606 , H01L29/42384 , H01L29/4908 , H01L29/66742 , H01L29/78684 , H01L51/0023 , H01L51/0048 , H01L51/0545 , H01L51/055
摘要： Transistor devices having nanoscale material-based channels (e.g., carbon nanotube or graphene channels) and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.
摘要翻译：提供具有基于纳米材料的通道（例如，碳纳米管或石墨烯通道）的晶体管器件及其制造技术。一方面，提供一种晶体管器件。晶体管器件包括衬底; 衬底上的绝缘体; 嵌入绝缘体中的局部底栅，其中栅极的顶表面与绝缘体的表面基本共面; 底栅上的局部栅极电介质; 在所述局部栅极电介质的至少一部分上的碳基纳米结构材料，其中所述碳基纳米结构材料的一部分用作所述器件的通道; 并且导电源极和漏极接触到用作器件的源极和漏极区域的沟道的相对侧上的碳基纳米结构材料的一个或多个部分。

7. 发明授权

US08642997B2 Transistor device with reduced gate resistance 有权
标题翻译：具有降低栅极电阻的晶体管器件
公开(公告)号：US08642997B2
公开(公告)日：2014-02-04
申请号：US13610381
申请日：2012-09-11
申请人： Shu-Jen Han , Alberto Valdes Garcia
发明人： Shu-Jen Han , Alberto Valdes Garcia
IPC分类号： H01L29/775
CPC分类号： H01L29/66742 , H01L29/42384 , H01L29/7781 , H01L29/78603 , H01L29/78636 , H01L29/78684
摘要： A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided.
摘要翻译：具有降低的栅极电阻的器件包括具有第一导电部分和形成为与第一导电部分电接触并且横向延伸超过第一导电部分延伸的第二导电部分的栅极结构。栅极结构嵌入电介质材料中，并且在第一导电部分上具有栅极电介质。沟道层设置在第一导电部分上。源极和漏极形成在沟道层的沟道区的相对端部上。还提供了形成栅极电阻降低的器件的方法。

8. 发明授权

US08593180B2 Circuit including a negative differential resistance (NDR) device having a graphene channel, and method of operating the circuit 失效
标题翻译：包括具有石墨烯通道的负差动电阻（NDR）装置的电路以及操作该电路的方法
公开(公告)号：US08593180B2
公开(公告)日：2013-11-26
申请号：US13418066
申请日：2012-03-12
申请人： Shu-Jen Han , Yu-Ming Lin , Yanqing Wu
发明人： Shu-Jen Han , Yu-Ming Lin , Yanqing Wu
IPC分类号： H03K19/02
CPC分类号： H01L29/42364 , H01L29/1606 , H01L29/1608 , H01L29/66431 , H01L29/7781 , H01L29/78684
摘要： A circuit includes a negative differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source which modulates a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance.
摘要翻译：电路包括包括栅极和石墨烯通道的负差分电阻（NDR）器件和调制栅极上的栅极电压的栅极电压源，使得通过石墨烯通道的电流呈现负的差分电阻。

9. 发明授权

US08455862B2 Self-aligned contacts in carbon devices 有权
标题翻译：碳装置中的自对准触点
公开(公告)号：US08455862B2
公开(公告)日：2013-06-04
申请号：US13562827
申请日：2012-07-31
申请人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L29/775
CPC分类号： H01L29/1606 , B82Y10/00 , H01L29/165 , H01L29/41733 , H01L29/41766 , H01L29/41775 , H01L29/66431 , H01L29/66742 , H01L29/7781 , H01L29/78 , H01L29/78684 , H01L51/0048
摘要： A semiconductor device includes a carbon layer disposed on a substrate, a gate stack disposed on a portion of the carbon layer, a first cavity defined by the carbon layer and the substrate, a second cavity defined by the carbon layer and the substrate, a source region including a first conductive contact disposed in the first cavity, a drain region including a second conductive contact disposed in the second cavity.
摘要翻译：半导体器件包括设置在基底上的碳层，设置在碳层的一部分上的栅极叠层，由碳层和衬底限定的第一腔，由碳层和衬底限定的第二腔，源区域，包括设置在第一腔中的第一导电触点，漏区，包括设置在第二腔中的第二导电触点。

10. 发明授权

US08354309B2 Method of providing threshold voltage adjustment through gate dielectric stack modification 有权
标题翻译：通过栅介质叠层修改提供阈值电压调整的方法
公开(公告)号：US08354309B2
公开(公告)日：2013-01-15
申请号：US13347014
申请日：2012-01-10
申请人： Brian J. Greene , Michael P. Chudzik , Shu-Jen Han , William K. Henson , Yue Liang , Edward P. Maciejewski , Myung-Hee Na , Edward J. Nowak , Xiaojun Yu
发明人： Brian J. Greene , Michael P. Chudzik , Shu-Jen Han , William K. Henson , Yue Liang , Edward P. Maciejewski , Myung-Hee Na , Edward J. Nowak , Xiaojun Yu
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L21/823462 , H01L21/28229 , H01L21/84 , H01L27/1203
摘要： Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.
摘要翻译：在掺杂半导体阱上形成多种类型的栅叠层。在掺杂半导体阱上形成高介电常数（高k）栅极电介质。在一个器件区域中形成金属栅极层，而在其他器件区域中暴露高k栅极电介质。在其他器件区域中形成具有不同厚度的阈值电压调节氧化物层。然后在阈值电压调整氧化物层上形成导电栅极材料层。一种类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质。其他类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质和具有不同厚度的第一阈值电压调整氧化物部分。具有不同阈值电压的场效应晶体管通过采用具有相同掺杂剂浓度的不同栅极电介质叠层和掺杂半导体阱来提供。

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