专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060043491A1 Electrostatic discharge protection device and method for its manufacture 有权
标题翻译：静电放电保护装置及其制造方法
公开(公告)号：US20060043491A1
公开(公告)日：2006-03-02
申请号：US11212000
申请日：2005-08-25
申请人： Shu-Chuan Lee , Ming-Hsiang Song , Shao-Chang Huang , Yi-Hsun Wu , Kuo-Feng Yu , Jian-Hsing Lee , Tong-Chern Ong
发明人： Shu-Chuan Lee , Ming-Hsiang Song , Shao-Chang Huang , Yi-Hsun Wu , Kuo-Feng Yu , Jian-Hsing Lee , Tong-Chern Ong
IPC分类号： H01L23/62
CPC分类号： H01L27/0255
摘要： Provided are an electrostatic discharge (ESD) protection device and a method for making such a device. In one example, the ESD protection device includes a Zener diode region formed in a substrate and an N-type metal oxide semiconductor (NMOS) device formed adjacent to the Zener diode region. The Zener diode region has two doped regions, a gate with a grounded potential positioned between the two doped regions, and two light doped drain (LDD) features formed in the substrate. One of the LDD features is positioned between each of the two doped regions and the gate. The NMOS device includes a source and a drain formed in the substrate and a second gate positioned between the source and the drain.
摘要翻译：提供一种静电放电（ESD）保护装置及其制造方法。在一个示例中，ESD保护装置包括形成在衬底中的齐纳二极管区域和邻近齐纳二极管区域形成的N型金属氧化物半导体（NMOS）器件。齐纳二极管区域具有两个掺杂区域，位于两个掺杂区域之间的接地电位的栅极和在衬底中形成的两个光掺杂漏极（LDD）特征。 LDD特征之一位于两个掺杂区域和栅极之间。 NMOS器件包括形成在衬底中的源极和漏极，以及位于源极和漏极之间的第二栅极。

2. 发明授权

US07420250B2 Electrostatic discharge protection device having light doped regions 有权
标题翻译：具有轻掺杂区域的静电放电保护器件
公开(公告)号：US07420250B2
公开(公告)日：2008-09-02
申请号：US11212000
申请日：2005-08-25
申请人： Shu-Chuan Lee , Ming-Hsiang Song , Shao-Chang Huang , Yi-Hsun Wu , Kuo-Feng Yu , Jian-Hsing Lee , Tong-Chern Ong
发明人： Shu-Chuan Lee , Ming-Hsiang Song , Shao-Chang Huang , Yi-Hsun Wu , Kuo-Feng Yu , Jian-Hsing Lee , Tong-Chern Ong
IPC分类号： H01L23/62
CPC分类号： H01L27/0255
摘要： Provided are an electrostatic discharge (ESD) protection device and a method for making such a device. In one example, the ESD protection device includes a Zener diode region formed in a substrate and an N-type metal oxide semiconductor (NMOS) device formed adjacent to the Zener diode region. The Zener diode region has two doped regions, a gate with a grounded potential positioned between the two doped regions, and two light doped drain (LDD) features formed in the substrate. One of the LDD features is positioned between each of the two doped regions and the gate. The NMOS device includes a source and a drain formed in the substrate and a second gate positioned between the source and the drain.
摘要翻译：提供一种静电放电（ESD）保护装置及其制造方法。在一个示例中，ESD保护装置包括形成在衬底中的齐纳二极管区域和邻近齐纳二极管区域形成的N型金属氧化物半导体（NMOS）器件。齐纳二极管区域具有两个掺杂区域，位于两个掺杂区域之间的接地电位的栅极和在衬底中形成的两个光掺杂漏极（LDD）特征。 LDD特征之一位于两个掺杂区域和栅极之间。 NMOS器件包括形成在衬底中的源极和漏极，以及位于源极和漏极之间的第二栅极。

3. 发明申请

US20050224883A1 Circuit design for increasing charge device model immunity 审中-公开
标题翻译：电路设计，增加充电器件抗干扰能力
公开(公告)号：US20050224883A1
公开(公告)日：2005-10-13
申请号：US10819759
申请日：2004-04-06
申请人： Shao-Chang Huang , Shu-Chuan Lee
发明人： Shao-Chang Huang , Shu-Chuan Lee
IPC分类号： H01L23/60 , H01L23/62 , H01L27/02
CPC分类号： H01L27/0255 , H01L23/60 , H01L24/06 , H01L2924/14 , H01L2924/00
摘要： A charge device model (CDM) immunity module used in a semiconductor circuit for CDM damage protection. The CDM immunity module comprises a CDM ground pad and a current directing device such as a diode coupled between the CDM ground pad and a substrate of at least one device in a core circuit to be protected, wherein the current directing device and the CDM ground pad dissipate CDM charges to avoid damage to an oxide layer of the protected device.
摘要翻译：用于CDM损伤保护的半导体电路中的充电装置模型（CDM）免疫模块。 CDM抗扰度模块包括CDM接地焊盘和电流引导器件，例如耦合在待保护的核心电路中的CDM接地焊盘和至少一个器件的衬底之间的二极管，其中电流引导器件和CDM接地焊盘消耗CDM电荷以避免损坏受保护器件的氧化物层。

4. 发明授权

US09385241B2 Electrostatic discharge (ESD) protection circuits, integrated circuits, systems, and methods for forming the ESD protection circuits 有权
标题翻译：静电放电（ESD）保护电路，集成电路，系统和形成ESD保护电路的方法
公开(公告)号：US09385241B2
公开(公告)日：2016-07-05
申请号：US12766186
申请日：2010-04-23
申请人： Shu-Chuan Lee , Kuo-Ji Chen , Wade Ma
发明人： Shu-Chuan Lee , Kuo-Ji Chen , Wade Ma
IPC分类号： H01L23/62 , H01L29/861 , H01L27/02 , H01L29/16 , H01L29/20
CPC分类号： H01L27/0262 , H01L27/0277 , H01L29/1608 , H01L29/2003 , H01L29/861
摘要： An electrostatic discharge (ESD) protection circuit coupled with an input/output (I/O) pad is provided. The ESD protection circuit includes a first field oxide device coupled between a first terminal that is capable of providing a first supply voltage and the I/O pad. The first field oxide device includes a drain end having a first type of dopant and a source end having the first type of dopant. The first field oxide device includes a first doped region having a second type of dopant disposed adjacent to the drain end of the first field oxide device and a second doped region having the second type of dopant disposed adjacent to the source end of the first field oxide device.
摘要翻译：提供与输入/输出（I / O）焊盘耦合的静电放电（ESD）保护电路。 ESD保护电路包括耦合在能够提供第一电源电压的第一端子和I / O焊盘之间的第一场氧化物装置。第一场氧化物器件包括具有第一类掺杂剂的漏极端和具有第一类掺杂剂的源极端。第一场氧化物器件包括具有邻近第一场氧化物器件的漏极端设置的第二类型掺杂物的第一掺杂区域和具有邻近第一场氧化物源极端的第二类型掺杂物的第二掺杂区域设备。

5. 发明授权

US06542346B1 High-voltage tolerance input buffer and ESD protection circuit 失效
标题翻译：高压容差输入缓冲器和ESD保护电路
公开(公告)号：US06542346B1
公开(公告)日：2003-04-01
申请号：US09586568
申请日：2000-06-02
申请人： Wei-Fan Chen , Shu-Chuan Lee , Ta-Lee Yu , Shi-Tron Lin
发明人： Wei-Fan Chen , Shu-Chuan Lee , Ta-Lee Yu , Shi-Tron Lin
IPC分类号： H02H322
CPC分类号： H01L27/0251 , H01L29/7436 , H01L29/87
摘要： A high-voltage tolerance input buffer and a high-voltage ESD protection circuit connected to a pad of an integrated circuit for preventing rapid gate oxide aging. The high-voltage tolerance input buffer of the present invention comprises a voltage-sharing circuit and a switch circuit, wherein the voltage-sharing circuit is connected between the pad and a power rail and generates a reference voltage not higher than the voltage of the pad. The switch circuit is connected to the voltage-sharing circuit and comprises a control gate to control the switching operation of the switch circuit according to the reference voltage. The present invention can be implemented to solve the rapid gate oxide aging problem without incurring any change in the original process flow by employing a voltage-sharing circuit.
摘要翻译：连接到集成电路的焊盘的高压公差输入缓冲器和高压ESD保护电路，用于防止快速栅极氧化物老化。本发明的高电压公差输入缓冲器包括电压共享电路和开关电路，其中电压共享电路连接在焊盘和电源轨之间，并产生不高于焊盘电压的参考电压。开关电路连接到分压电路，并包括控制栅极，以根据参考电压来控制开关电路的开关操作。本发明可以实现以解决快速栅极氧化物老化问题，而不会通过采用电压共享电路而引起原始工艺流程的任何变化。

6. 发明授权

US06229183B1 ESD damage immunity buffer 失效
标题翻译： ESD损伤免疫缓冲液
公开(公告)号：US06229183B1
公开(公告)日：2001-05-08
申请号：US09460590
申请日：1999-12-14
申请人： Shu-Chuan Lee
发明人： Shu-Chuan Lee
IPC分类号： H01L2362
CPC分类号： H01L27/0266 , H01L27/0259 , H01L27/0288
摘要： The present invention discloses an ESD damage immunity buffer, comprising: a gate, a first doped region, a second doped region, a third doped region, and a resist layer. The ESD damage immunity buffer, which is in parallel with an ESD protection circuit, is connected to a pad and the circuit grounding node. The gate is formed on the semiconductor substrate, and the first doped region and the second doped region are formed adjacent to the region below the gate in the semiconductor substrate and electrically coupled to the ground. The third doped region is formed in the semiconductor substrate and electrically coupled to the pad. Further, a resist layer is formed upon the semiconductor substrate and connects the third doped region to the second doped region, wherein said resist layer ensures a triggering of the ESD protection circuit prior to the ESD damage immunity buffer during an ESD event.
摘要翻译：本发明公开了一种ESD损伤抗扰度缓冲器，包括：栅极，第一掺杂区域，第二掺杂区域，第三掺杂区域和抗蚀剂层。与ESD保护电路并联的ESD损伤抗扰度缓冲器连接到焊盘和电路接地节点。栅极形成在半导体衬底上，并且第一掺杂区域和第二掺杂区域形成在半导体衬底中与栅极下方的区域相邻并且电耦合到地面。第三掺杂区域形成在半导体衬底中并电耦合到焊盘。此外，在半导体衬底上形成抗蚀剂层并且将第三掺杂区域连接到第二掺杂区域，其中所述抗蚀剂层确保在ESD事件期间在ESD损坏抗扰度缓冲器之前触发ESD保护电路。

7. 发明授权

US06538288B2 ESD protection device with island-like distributed p+ diffusion regions 失效
公开(公告)号：US06538288B2
公开(公告)日：2003-03-25
申请号：US09725220
申请日：2000-11-29
申请人： Shu-Chuan Lee , Yu-Chen Lin
发明人： Shu-Chuan Lee , Yu-Chen Lin
IPC分类号： H01L2362
CPC分类号： H01L27/0262 , H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection structure for an integrated circuit constructed on a substrate of a first type is provided to includes a plurality of island-like distributed diffusion regions. The protection structure includes a semiconductor controlled rectifier (SCR), an MOS transistor and a plurality of island-like distributed diffusion regions of the first type. The semiconductor controlled rectifier is constructed on the base region and coupled to the integrated circuit. The SCR includes a first region of a second type formed next to the base region, a second region of the first type formed in the first region, and a third region of the second type formed in the base region. The MOS transistor has a drain coupled to the bonding pad or a VDD bus, and a gate and a source both coupled to a reference ground. The plurality of island-like distributed diffusion regions of the first type are formed in the base region and each is coupled to the reference ground.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式