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1. 发明申请

US20080247233A1 NON-VOLATILE MEMORY DEVICE, NON-VOLATILE MEMORY SYSTEM AND CONTROL METHOD FOR THE NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件，非易失性存储器系统和非易失性存储器件的控制方法
公开(公告)号：US20080247233A1
公开(公告)日：2008-10-09
申请号：US12058471
申请日：2008-03-28
申请人： Shozo Kawabata , Sooyong Park
发明人： Shozo Kawabata , Sooyong Park
IPC分类号： G11C16/04 , G11C8/00 , G11C5/14
CPC分类号： G11C16/0491 , G11C16/26
摘要： A nonvolatile memory device which can reduce consumption current and shorten access time and a control method thereof is provided. The nonvolatile memory device 1 comprises a booster controller circuit 10, a booster circuit 20, a level-shifting circuit 30, a Y-decoder 40, and a main circuit 50. A NAND gate ND1, a NOR gate NR1, and a NOR gate NR2 provided in the booster controller circuit 10 output kick signals KICK0 to KICK2. The booster circuit 20 comprises boosting systems B0, B1, B2 which respectively receive the kick signals KICK0, KICK1, and KICK2. The kick signals KICK0 and KICK1 outputted from the NAND gate ND1 and the NOR gate NR1 make transition to high level in accordance with the transition of column address coladd from address 7 to 8. Therefore, the boosting system B0 is activated in addition to the boosting system B1.
摘要翻译：提供一种能够降低消耗电流并缩短访问时间的非易失性存储装置及其控制方法。非易失性存储器件1包括升压控制器电路10，升压电路20，电平移位电路30，Y解码器40和主电路50。在升压控制电路10中设置的NAND门ND1，NOR门NR1，NOR门NR2输出启动信号KICK0〜KICK2。升压电路20包括分别接收启动信号KICK 0，KICK 1和KICK 2的升压系统B 0，B 1，B 2。从与非门ND 1和或非门NR 1输出的触发信号KICK 0和KICK 1根据从地址7到8的列地址的转换转换到高电平。因此，升压系统B 0除了升压系统B1之外也被激活。

2. 发明授权

US07859914B2 Non-volatile memory device, non-volatile memory system and control method for the non-volatile memory device in which driving ability of a selector transistor is varied 有权
标题翻译：用于非易失性存储器件的非易失性存储器件，非易失性存储器系统和控制方法，其中选择晶体管的驱动能力变化
公开(公告)号：US07859914B2
公开(公告)日：2010-12-28
申请号：US12058471
申请日：2008-03-28
申请人： Shozo Kawabata , Sooyong Park
发明人： Shozo Kawabata , Sooyong Park
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0491 , G11C16/26
摘要： The control method includes a step of varying driving ability of a selector transistor which selects a diffusion layer in a selected memory cell and a diffusion layer of at least one non-selected memory cell which adjoins to the selected memory cell when the selected memory cell makes transition from a memory cell at one end to a memory cell at other end within a memory block.
摘要翻译：控制方法包括：当所选择的存储单元产生时，选择晶体管的选择晶体管的驱动能力的步骤，所述选择晶体管选择所选择的存储单元中的扩散层和至少一个与所选存储单元相邻的未选择的存储单元的扩散层从一端的存储单元转换到存储器块内另一端的存储单元。

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