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1. 发明授权

US07796457B2 Motherboard with voltage regulator supporting DDR2 memory modules and DDR3 memory modules 有权
标题翻译：带稳压器的主板，支持DDR2内存模块和DDR3内存模块
公开(公告)号：US07796457B2
公开(公告)日：2010-09-14
申请号：US11766105
申请日：2007-06-21
申请人： Shou-Kuo Hsu , Duen-Yi Ho , Cheng-Shien Li
发明人： Shou-Kuo Hsu , Duen-Yi Ho , Cheng-Shien Li
IPC分类号： G11C5/14
CPC分类号： G06F1/26
摘要： An exemplary motherboard includes a first slot arranged for mounting a first type of memory, a second slot arranged for mounting a second type of memory, a voltage regulator electronically connected to the first slot and the second slot, and a serial presence detect (SPD) unit connected to the voltage regulator. The first memory and the second memory alternatively mounted on the motherboard, the SPD detects which type of memory is mounted on the motherboard, and the voltage regulator outputs voltages suitable for the type of the memory mounted on the motherboard according to a detection result of the SPD.
摘要翻译：示例性主板包括布置用于安装第一类型存储器的第一槽，布置用于安装第二类型存储器的第二槽，电连接到第一槽和第二槽的电压调节器，以及串联存在检测（SPD）单元连接到电压调节器。第一存储器和第二存储器交替地安装在母板上，SPD检测在主板上安装哪种类型的存储器，并且电压调节器根据检测结果输出适合安装在母板上的存储器类型的电压 SPD。

2. 发明授权

US07813208B2 Motherboard with voltage regulator for supporting DDR2 memory modules and DDR3 memory modules 有权
标题翻译：具有稳压器的主板，用于支持DDR2内存模块和DDR3内存模块
公开(公告)号：US07813208B2
公开(公告)日：2010-10-12
申请号：US11965753
申请日：2007-12-28
申请人： Shou-Kuo Hsu , Duen-Yi Ho , Cheng-Shien Li
发明人： Shou-Kuo Hsu , Duen-Yi Ho , Cheng-Shien Li
IPC分类号： G11C5/14
CPC分类号： G06F13/4072 , G06F13/4239 , H05K1/0262 , H05K1/14 , H05K2201/044 , H05K2201/09954 , H05K2201/10159
摘要： An exemplary motherboard includes a driving module, at least two first slots arranged for mounting two first type of memories, at least two second slots arranged for mounting two second type of memories, and a voltage regulator. The driving module is electronically connected to the at least two first slots, the at least two second slots, and the voltage regulator in turn via a channel. The first type of memories and the second type of memories are alternatively mounted on the motherboard, the voltage regulator detects which type memory is currently mounted on the motherboard and outputs voltages suitable for the type of memory mounted on the motherboard accordingly.
摘要翻译：示例性主板包括驱动模块，布置成用于安装两个第一类型存储器的至少两个第一槽，布置成安装两个第二类型存储器的至少两个第二槽和电压调节器。驱动模块通过通道电连接到至少两个第一插槽，至少两个第二插槽和电压调节器。第一类型的存储器和第二类型的存储器交替地安装在母板上，电压调节器检测当前安装在母板上的哪种类型的存储器，并相应地输出适合于安装在母板上的存储器类型的电压。

3. 发明授权

US07817487B2 Motherboard with voltage regulator for supporting DDR2 memory modules and DDR3 memory modules 有权
标题翻译：具有稳压器的主板，用于支持DDR2内存模块和DDR3内存模块
公开(公告)号：US07817487B2
公开(公告)日：2010-10-19
申请号：US11952140
申请日：2007-12-07
申请人： Shou-Kuo Hsu , Duen-Yi Ho , Cheng-Shien Li
发明人： Shou-Kuo Hsu , Duen-Yi Ho , Cheng-Shien Li
IPC分类号： G11C5/14
CPC分类号： G06F1/26 , G11C5/04 , G11C5/147 , H05K1/0262 , H05K1/14 , H05K2201/044 , H05K2201/09954 , H05K2201/10159
摘要： An exemplary motherboard includes a driving module, a first slot module arranged for mounting a first type of memory and connected to the driving module via a first channel, a second slot module arranged for mounting a second type of memory and connected to the driving module via a second channel, and a voltage regulator electronically connected to the first slot module and the second slot module. The first memory and the second memory are alternatively mounted on the motherboard, the voltage regulator detects which type memory is currently mounted on the motherboard and outputs voltages suitable for the type of the memory mounted on the motherboard accordingly.
摘要翻译：示例性主板包括驱动模块，布置成用于安装第一类型存储器并经由第一通道连接到驱动模块的第一插槽模块，布置成用于安装第二类型存储器并连接到驱动模块的第二插槽模块，其经由第二通道和电连接到第一插槽模块和第二插槽模块的电压调节器。第一存储器和第二存储器替代地安装在母板上，电压调节器检测当前安装在母板上的哪种类型的存储器，并相应地输出适合安装在母板上的存储器类型的电压。

4. 发明授权

US07752348B2 Motherboard for supporting different types of memories 失效
标题翻译：主板支持不同类型的记忆
公开(公告)号：US07752348B2
公开(公告)日：2010-07-06
申请号：US11952139
申请日：2007-12-07
申请人： Chun-Sheng Chen , Shou-Kuo Hsu , Cheng-Shien Li , Duen-Yi Ho , Yu-Chang Pai
发明人： Chun-Sheng Chen , Shou-Kuo Hsu , Cheng-Shien Li , Duen-Yi Ho , Yu-Chang Pai
IPC分类号： G06F3/00 , H05K7/10
CPC分类号： H05K1/0295 , H05K1/0262 , H05K1/14 , H05K2201/044 , H05K2201/09954 , H05K2201/10159
摘要： A motherboard includes a first slot arranged for mounting a first type of memory, a second slot arranged for mounting a second type of memory, and a voltage regulating circuit electronically connected to the first slot and the second slot. The first memory and the second memory are alternatively mounted on the motherboard, the voltage regulating circuit detects which type memory is currently mounted on the motherboard and outputs voltages suitable for the type of the memory mounted on the motherboard accordingly.
摘要翻译：主板包括布置成用于安装第一类型存储器的第一插槽，布置用于安装第二类型存储器的第二插槽以及电连接到第一插槽和第二插槽的电压调节电路。第一存储器和第二存储器替代地安装在母板上，电压调节电路检测当前安装在母板上的哪种类型的存储器，并相应地输出适合安装在母板上的存储器类型的电压。

5. 发明授权

US08446436B2 Overdrive topology structure for transmission of RGB Signal 失效
标题翻译：用于传输RGB信号的过载拓扑结构
公开(公告)号：US08446436B2
公开(公告)日：2013-05-21
申请号：US12483260
申请日：2009-06-12
申请人： Shou-Kuo Hsu , Yu-Chang Pai , Cheng-Shien Li , Jia-Chi Chen
发明人： Shou-Kuo Hsu , Yu-Chang Pai , Cheng-Shien Li , Jia-Chi Chen
IPC分类号： G09G5/10 , H01P3/00
CPC分类号： H04L25/0278 , G09G5/04 , G09G2300/0426
摘要： An overdrive topology structure for transmission of a RGB signal includes a signal sending terminal, a signal receiving terminal, and a transmission line to transmit the RGB signal from the signal sending terminal to the signal receiving terminal. The transmission line is divided into a number of section transmission lines. A node is formed between every two section transmission lines. An impedance of a first section transmission line approaching to the signal sending terminal is less than an impedance of a second section transmission line approaching to the first section transmission line to overdrive the RGB signal at a first node between the first and second section transmission lines. At least one node except the first node is grounded via a resistor. An equivalent resistance of the resistor is equal to a resistance of the first resistor.
摘要翻译：用于传输RGB信号的过驱动拓扑结构包括信号发送端，信号接收端和传输线，以将RGB信号从信号发送端发送到信号接收端。传输线被分成多个部分传输线。在每两段传输线之间形成节点。接近信号发送端的第一部分传输线的阻抗小于接近第一部分传输线的第二部分传输线的阻抗，以在第一和第二部分传输线之间的第一节点处过驱动RGB信号。除第一个节点之外的至少一个节点通过电阻器接地。电阻器的等效电阻等于第一电阻器的电阻。

6. 发明授权

US08018296B2 Printed circuit board having a plurality of angled differential pairs of transmission lines 失效
标题翻译：具有多个成对的差分传输线对的印刷电路板
公开(公告)号：US08018296B2
公开(公告)日：2011-09-13
申请号：US12205146
申请日：2008-09-05
申请人： Cheng-Shien Li , Yung-Chieh Chen , Shou-Kuo Hsu
发明人： Cheng-Shien Li , Yung-Chieh Chen , Shou-Kuo Hsu
IPC分类号： H01P3/08
CPC分类号： H05K1/0245 , H05K1/0366 , H05K2201/029 , H05K2201/09236 , H05K2201/09263 , H05K2201/09272
摘要： A printed circuit board includes a plurality of differential pairs arranged thereon side-by-side. Each differential pair includes two transmission lines. Each transmission line includes a plurality of sections of equal length. Every two adjacent sections in each transmission line meet at an angle, and all angles are equal. The length of each section is determined by dividing the distance between two corresponding angles of the two transmission lines of each differential pair by the cosine of half of the angle.
摘要翻译：印刷电路板包括并排布置的多个差分对。每个差分对包括两条传输线。每个传输线包括多个相等长度的部分。每个传输线中的每两个相邻部分以一定角度相交，并且所有角度相等。每个部分的长度通过将每个差分对的两个传输线的两个对应角度之间的距离除以角度的一半的余弦来确定。

7. 发明授权

US07634371B2 System and method for analyzing jitter of signals 有权
标题翻译：用于分析信号抖动的系统和方法
公开(公告)号：US07634371B2
公开(公告)日：2009-12-15
申请号：US11212338
申请日：2005-08-26
申请人： Cheng-Shien Li , Shou-Kuo Hsu
发明人： Cheng-Shien Li , Shou-Kuo Hsu
IPC分类号： G01R13/00 , H04B3/46
CPC分类号： G06F17/5036 , G01R31/31709
摘要： The present invention provides a system and a method for analyzing jitter of various signals including measurement signals and simulation signals. The method includes the steps of: (a) obtaining a signal file; (b) identifying a type of the signal file; (c) defining a jitter analysis mode from a phase jitter mode, a periodic jitter mode and a cycle jitter mode; (d) obtaining an n-bit differential signal from the signal file; (e) rebuilding an ideal clock based on the differential signal by means of performing a Minimum Deviation Algorithm (MDA); (f) calculating and analyzing jitter of the differential signal according to the ideal clock by means of performing the MDA; and (g) generating and outputting a jitter analysis wave and jitter analysis results according to the defined jitter analysis mode.
摘要翻译：本发明提供了一种用于分析包括测量信号和模拟信号在内的各种信号的抖动的系统和方法。该方法包括以下步骤：（a）获取信号文件; （b）识别信号文件的类型; （c）从相位抖动模式，周期抖动模式和周期抖动模式定义抖动分析模式; （d）从信号文件获得n位差分信号; （e）通过执行最小偏差算法（MDA），重建基于差分信号的理想时钟; （f）通过执行MDA，根据理想时钟计算和分析差分信号的抖动; 和（g）根据定义的抖动分析模式生成和输出抖动分析波和抖动分析结果。

8. 发明授权

US07581200B2 System and method for analyzing length differences in differential signal paths 失效
标题翻译：分析差分信号路径长度差异的系统和方法
公开(公告)号：US07581200B2
公开(公告)日：2009-08-25
申请号：US11552975
申请日：2006-10-26
申请人： Shou-Kuo Hsu , Cheng-Shien Li
发明人： Shou-Kuo Hsu , Cheng-Shien Li
IPC分类号： G06F17/50
CPC分类号： G01R31/31725 , G01R31/318357 , G06F17/5036
摘要： A method for analyzing length differences in differential signal paths includes: loading a design file of the differential signal paths from a storage device (9); simulating the differential signal paths based on the design file; dividing simulated differential signal paths into a plurality of segments by impedance division positions that show impedance discontinuity; predefining an acceptable length difference limit for each divided segment, and calculating an real length difference for each divided segment; comparing the real length difference with the acceptable length difference limit correspondingly to generate a plurality of analyzed results corresponding to the plurality of divided segments; selecting one or more compared segments to check analyzed results of selected segments; and locating the selected segments in the simulated differential signal paths, and generating analyzed information comprising analyzed results of the selected segments. A related system is also disclosed.
摘要翻译：用于分析差分信号路径中的长度差的方法包括：从存储设备（9）加载差分信号路径的设计文件; 基于设计文件模拟差分信号路径; 通过示出阻抗不连续性的阻抗分割位置将模拟差分信号路径分割成多个段; 预先定义每个分割段的可接受长度差异限制，以及计算每个分割段的实际长度差; 将实际长度差与可接受的长度差极限相对应地对应地生成对应于多个分割段的多个分析结果; 选择一个或多个比较的段以检查所选段的分析结果; 以及将所选择的段定位在所述模拟的差分信号路径中，以及生成包括所选段的分析结果的分析信息。还公开了相关系统。

9. 发明授权

US08418357B2 Printed circuit board layout method 有权
标题翻译：印刷电路板布局方法
公开(公告)号：US08418357B2
公开(公告)日：2013-04-16
申请号：US12329614
申请日：2008-12-07
申请人： Yung-Chieh Chen , Cheng-Shien Li , Shou-Kuo Hsu
发明人： Yung-Chieh Chen , Cheng-Shien Li , Shou-Kuo Hsu
IPC分类号： H05K3/30 , H01R43/00
CPC分类号： H05K1/0295 , H05K1/0231 , H05K1/0237 , H05K1/0243 , H05K1/113 , H05K2201/09236 , H05K2201/09954 , H05K2201/10545 , H05K2201/10636 , H05K2201/10689 , Y02P70/611 , Y10T29/49117 , Y10T29/4913
摘要： A printed circuit board layout method includes the following steps. Providing a printed circuit board with a first layout layer and a second layout layer. Disposing a pair of first conducting portions on the first layout layer to electrically couple to a control chip. Sequentially disposing a pair of second conducting portions, a pair of third conducting portions, and a pair of fourth conducting portions on the second layout layer. Providing a pair of connecting portions to connect the first conducting portions and the third conducting portions. Electrically connecting an electronic device to the second conducting portions, and providing a first and second components are coupled with the third and fourth conducting portions, or electrically coupling the electronic device to the fourth conducting portions, and providing the first and the second components are coupled with the second and third conducting portions.
摘要翻译：印刷电路板布局方法包括以下步骤。提供具有第一布局层和第二布局层的印刷电路板。在第一布局层上布置一对第一导电部分以电耦合到控制芯片。在第二布局层上顺序地布置一对第二导电部分，一对第三导电部分和一对第四导电部分。提供一对连接部分以连接第一导电部分和第三导电部分。将电子设备电连接到第二导电部分，以及提供第一和第二部件与第三和第四导电部分耦合，或将电子器件电耦合到第四导电部分，并且提供第一和第二部件耦合具有第二和第三导电部分。

10. 发明授权

US07444255B2 System and method for analyzing lengths of branches of signal paths 失效
标题翻译：用于分析信号路径分支长度的系统和方法
公开(公告)号：US07444255B2
公开(公告)日：2008-10-28
申请号：US11768922
申请日：2007-06-27
申请人： Shou-Kuo Hsu , Chia-Nan Pai , Cheng-Shien Li
发明人： Shou-Kuo Hsu , Chia-Nan Pai , Cheng-Shien Li
IPC分类号： G01R27/28
CPC分类号： G06F17/5036 , G01R31/025 , G01R31/041
摘要： A system for analyzing lengths of branches of signal paths is disclosed. The system includes: a signal path naming module for naming all signal paths of a PCB; a signal path group selecting module for selecting a group of signal paths to be analyzed from the database; a signal path selecting module for selecting signal paths to be analyzed from the group of signal paths; a branch searching module for analyzing the selected signal paths, to search passive circuit components and external circuits connected to the selected signal paths for corresponding branches of the selected signal paths; a branch length calculating module for calculating a length of each branch; and a branch length comparing module for comparing each calculated branch length with a corresponding predefined maximal branch length to determine whether the calculated branch length is more than the predefined maximal branch length. A related method is also disclosed.
摘要翻译：公开了一种用于分析信号路径的分支长度的系统。该系统包括：用于命名PCB的所有信号路径的信号路径命名模块; 信号路径组选择模块，用于从数据库中选择要分析的一组信号路径; 信号路径选择模块，用于从信号路径组中选择要分析的信号路径; 用于分析所选择的信号路径的分支搜索模块，搜索与所选择的信号路径连接的无源电路组件和外部电路用于所选择的信号路径的相应分支; 分支长度计算模块，用于计算每个分支的长度; 以及分支长度比较模块，用于将每个计算的分支长度与相应的预定义的最大分支长度进行比较，以确定所计算的分支长度是否大于预定的最大分支长度。还公开了相关方法。

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