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1. 发明授权

US4716526A Multiprocessor system 失效
标题翻译：多处理器系统
公开(公告)号：US4716526A
公开(公告)日：1987-12-29
申请号：US622455
申请日：1984-06-20
申请人： Shosuke Mori , Atsushi Sakurai , Satoshi Aoki , Tatsuya Suzuki
发明人： Shosuke Mori , Atsushi Sakurai , Satoshi Aoki , Tatsuya Suzuki
IPC分类号： G06F9/46 , G06F9/38 , G06F13/40 , G06F15/16 , G06F15/177
CPC分类号： G06F13/409
摘要： A multiprocessor system used, for example, in a personal computer, wherein different types of microprocessors are used independently of the architecture of each microprocessor. The system includes a control register, a control circuit, and a common peripheral circuit mounted, for example, on a main board, and a plurality of kinds of microprocessors each mounted, for example, on a sub-board connected to the main board. The control circuit transmits a halt request signal to a first microprocessor which is currently operating, in response to coincidence between an output signal of the control register and the status signal indicating that a second microprocessor is in a halt condition, when the output signal of the control register is changed by the first microprocessor. Then, the control circuit releases a halt request signal applied to the second microprocessor in response to coincidence between a status signal indicating that the first microprocessor has entered into a halt condition and the output signal of the control register.
摘要翻译：例如，在个人计算机中使用的多处理器系统，其中独立于每个微处理器的架构使用不同类型的微处理器。该系统包括例如安装在主板上的控制寄存器，控制电路和公共外围电路以及各自安装在例如连接到主板的子板上的多种微处理器。当控制电路的输出信号响应于控制寄存器的输出信号和表示第二微处理器处于停止状态的状态信号之间的一致时，控制电路向当前操作的第一微处理器发送暂停请求信号控制寄存器被第一个微处理器改变。然后，响应于指示第一微处理器进入停止状态的状态信号与控制寄存器的输出信号之间的一致，控制电路释放施加到第二微处理器的暂停请求信号。

2. 发明授权

US4684935A Combined graphic and textual display system 失效
标题翻译：组合图形和文字显示系统
公开(公告)号：US4684935A
公开(公告)日：1987-08-04
申请号：US552974
申请日：1983-11-17
申请人： Kiminori Fujisaku , Makoto Awaga , Shosuke Mori
发明人： Kiminori Fujisaku , Makoto Awaga , Shosuke Mori
IPC分类号： G06F3/153 , G06T11/20 , G09G1/06 , G09G3/36 , G09G5/02 , G09G5/40 , G09G1/00
CPC分类号： G06F3/153 , G09G3/3611 , G09G5/026 , G09G5/40 , G09G2360/04
摘要： A display system comprises a first image memory storing first image data, a second image memory storing second image data operable independently from the first image memory, a display selection and combination circuit, and two display units. The display selection and combination circuit connected to the first and second image memories is formed such that each of the display units displays a combination of data from the image memories according to a display request. Normally, the display units are cathode ray tubes or liquid crystal displays. Usually, one of the first and second image memories stores character information, such as letters and numerals, and the other stores graphic information, such as figures and curves.
摘要翻译：显示系统包括存储第一图像数据的第一图像存储器，存储独立于第一图像存储器操作的第二图像数据的第二图像存储器，显示选择和组合电路以及两个显示单元。连接到第一和第二图像存储器的显示选择和组合电路形成为使得每个显示单元根据显示请求显示来自图像存储器的数据的组合。通常，显示单元是阴极射线管或液晶显示器。通常，第一和第二图像存储器中的一个存储诸如字母和数字的字符信息，而另一个存储诸如图形和曲线的图形信息。

3. 发明授权

US4626986A Processor having plural initial loading programs for loading different operating systems 失效
标题翻译：处理器具有用于加载不同操作系统的多个初始加载程序
公开(公告)号：US4626986A
公开(公告)日：1986-12-02
申请号：US827678
申请日：1986-02-10
申请人： Shosuke Mori
发明人： Shosuke Mori
IPC分类号： G06F1/00 , G06F9/445 , G06F12/06 , G06F13/00 , G06F9/40
CPC分类号： G06F9/441
摘要： An information processor with a read only memory ROM stores a plurality of initial program loader (IPL) programs. The ROM memory has address inputs divided into two parts used to access each IPL program. One part of the address inputs of the ROM memory is connected to an address bus from a central processing unit (CPU) in order to be used to access the contents of one of the programs. The other part of the address inputs of said ROM memory is connected to an IPL setting part or switching which sets or selects a desired one of said plurality of IPL programs. The IPL setting part includes a plurality of switches connected to upper bit terminals of the ROM address inputs.
摘要翻译：具有只读存储器ROM的信息处理器存储多个初始程序加载器（IPL）程序。 ROM存储器具有分成两部分的地址输入，用于访问每个IPL程序。 ROM存储器的地址输入的一部分被连接到来自中央处理单元（CPU）的地址总线，以便用于访问其中一个程序的内容。所述ROM存储器的地址输入的另一部分连接到设置或选择所述多个IPL程序中期望的一个的IPL设置部分或切换。 IPL设置部分包括连接到ROM地址输入的高位端的多个开关。

4. 发明授权

US4574347A Data processing apparatus for performing high-speed arithmetic operations 失效
标题翻译：用于执行高速算术运算的数据处理装置
公开(公告)号：US4574347A
公开(公告)日：1986-03-04
申请号：US549472
申请日：1983-11-07
申请人： Shosuke Mori , Makoto Awaga , Kiminori Fujisaku , Mitsuru Yamauchi , Hitoshi Ono
发明人： Shosuke Mori , Makoto Awaga , Kiminori Fujisaku , Mitsuru Yamauchi , Hitoshi Ono
IPC分类号： G06F3/153 , G06F9/38 , G06T1/20 , G09G5/00 , G09G5/32 , G09G5/39 , G09G5/395 , G06F7/38
CPC分类号： G06F9/3877
摘要： A data processing apparatus includes a CPU, a memory, and logic operation hardware. When a predetermined instruction code is identified, the logic operation hardware executes an arithmetic operation using data stored in the memory, while the CPU processes the same data. The logic operation hardware then writes the result of the arithmetic operation instead of the data processed by the CPU.
摘要翻译：数据处理装置包括CPU，存储器和逻辑运算硬件。当识别出预定的指令代码时，逻辑运算硬件使用存储在存储器中的数据执行算术运算，而CPU处理相同的数据。然后，逻辑运算硬件写入算术运算的结果，而不是由CPU处理的数据。

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