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1. 发明申请

US20090222225A1 IDDQ TEST APPARATUS AND TEST METHOD 失效
标题翻译： IDDQ测试装置和测试方法
公开(公告)号：US20090222225A1
公开(公告)日：2009-09-03
申请号：US12391210
申请日：2009-02-23
申请人： Shoji Kojima , Yasuo Furukawa
发明人： Shoji Kojima , Yasuo Furukawa
IPC分类号： G01R19/00 , G06F17/18
CPC分类号： G01R31/3008
摘要： Multiple non-defective samples of a DUT are selected. A quiescent power supply current (IDDQ) is measured for each of test vectors which are switched, for each of the non-defective samples. Statistical IDDQ values are measured in increments of the test vectors, and first array data is created including identifiers for the test vectors and the statistical IDDQs as elements. The first array data is sorted using the IDDQ value as a key so as to create second array data. The difference in quiescent power supply current is calculated by making difference between adjacent current elements of the second array data, so as to create third array data including the identifiers for the test vectors and the differences of current value as the elements.The third array data is sorted using the difference in current value as a key, and creates fourth array data.
摘要翻译：选择DUT的多个无缺陷样本。针对每个无缺陷样本切换的每个测试向量测量静态电源电流（IDDQ）。以测试向量的增量测量统计IDDQ值，并且创建包括测试向量和统计IDDQ作为元素的标识符的第一阵列数据。使用IDDQ值作为关键字对第一个数组数据进行排序，以创建第二个数组数据。通过使第二阵列数据的相邻电流元件之间的差异来计算静态电源电流的差异，从而创建包括测试矢量的标识符和当前值的差异作为元件的第三阵列数据。使用当前值的差作为关键字对第三个数组数据进行排序，并创建第四个数组数据。

2. 发明授权

US08195411B2 IDDQ test apparatus and test method 失效
标题翻译： IDDQ测试仪器和测试方法
公开(公告)号：US08195411B2
公开(公告)日：2012-06-05
申请号：US12391210
申请日：2009-02-23
申请人： Shoji Kojima , Yasuo Furukawa
发明人： Shoji Kojima , Yasuo Furukawa
IPC分类号： G01R19/00 , G01R31/02 , G01R31/26
CPC分类号： G01R31/3008
摘要： Multiple non-defective samples of a DUT are selected. A quiescent power supply current (IDDQ) is measured for each of test vectors which are switched, for each of the non-defective samples. Statistical IDDQ values are measured in increments of the test vectors, and first array data is created including identifiers for the test vectors and the statistical IDDQs as elements. The first array data is sorted using the IDDQ value as a key so as to create second array data. The difference in quiescent power supply current is calculated by making difference between adjacent current elements of the second array data, so as to create third array data including the identifiers for the test vectors and the differences of current value as the elements. The third array data is sorted using the difference in current value as a key, and creates fourth array data.
摘要翻译：选择DUT的多个无缺陷样本。针对每个无缺陷样本切换的每个测试向量测量静态电源电流（IDDQ）。以测试向量的增量测量统计IDDQ值，并且创建包括测试向量和统计IDDQ作为元素的标识符的第一阵列数据。使用IDDQ值作为关键字对第一个数组数据进行排序，以创建第二个数组数据。通过使第二阵列数据的相邻电流元件之间的差异来计算静态电源电流的差异，从而创建包括测试矢量的标识符和当前值的差异作为元件的第三阵列数据。使用当前值的差作为关键字对第三个数组数据进行排序，并创建第四个数组数据。

3. 发明授权

US08536887B2 Probe circuit, multi-probe circuit, test apparatus, and electric device 失效
标题翻译：探头电路，多探头电路，测试仪器和电气设备
公开(公告)号：US08536887B2
公开(公告)日：2013-09-17
申请号：US12830938
申请日：2010-07-06
申请人： Yasuo Furukawa
发明人： Yasuo Furukawa
IPC分类号： G01R31/3187
CPC分类号： G01R31/31922
摘要： A probe circuit is provided in an electronic device that includes a circuit which is under test and outputs a response signal corresponding to an input signal in synchronization with an operation clock. The probe circuit includes a sampling clock supplying section that outputs a sampling clock having a predetermined frequency, and a sampling section that outputs, outside the electronic device, a probe output signal of which frequency is lower than a frequency of the response signal and which corresponds to a sampling result obtained by sampling the response signal using the sampling clock. The response signal has a prescribed signal pattern repeated with a predetermined recurrence period, and the sampling clock supplying section outputs the sampling clock of which relative phase with respect to the signal pattern sequentially changes in each recurrence period.
摘要翻译：探针电路设置在电子设备中，该电子设备包括被测试的电路，并且与操作时钟同步地输出与输入信号相对应的响应信号。探针电路包括：采样时钟提供部，其输出具有预定频率的采样时钟;以及采样部，其在电子设备外部输出频率低于所述响应信号的频率的探测输出信号，并且对应于通过使用采样时钟对响应信号进行采样而获得的采样结果。响应信号具有以预定的重复周期重复的规定信号图案，并且采样时钟提供部分输出相对于信号模式的相对相位在每个复现周期中顺序变化的采样时钟。

4. 发明授权

US08525714B2 Test apparatus and test method for A/D converter 有权
标题翻译： A / D转换器的测试仪器和测试方法
公开(公告)号：US08525714B2
公开(公告)日：2013-09-03
申请号：US13414611
申请日：2012-03-07
申请人： Koji Asami , Yasuo Furukawa
发明人： Koji Asami , Yasuo Furukawa
IPC分类号： H03M1/06
CPC分类号： H03M1/109 , H03M1/12
摘要： A test apparatus configured to test an N-bit (N represents an integer) A/D converter is provided. A voltage generating unit outputs a 2N-valued analog voltage to the A/D converter. A capture unit captures an output code of the A/D converter for each level. A signal processing unit compares the output code captured for each level with the corresponding expected value code, corrects the value of the analog voltage for each level based upon the comparison result, and outputs the corrected analog voltage to the voltage generating unit.
摘要翻译：提供了一种被配置为测试N位（N表示整数）A / D转换器的测试装置。电压产生单元向A / D转换器输出2N值的模拟电压。捕获单元捕获每个级别的A / D转换器的输出代码。信号处理单元将每个级别捕获的输出代码与相应的预期值代码进行比较，根据比较结果对每个级别的模拟电压值进行校正，并将校正的模拟电压输出到电压产生单元。

5. 发明申请

US20120229314A1 TEST APPARATUS AND TEST METHOD FOR A/D CONVERTER 有权
标题翻译： A / D转换器的测试装置和测试方法
公开(公告)号：US20120229314A1
公开(公告)日：2012-09-13
申请号：US13414611
申请日：2012-03-07
申请人： Koji Asami , Yasuo Furukawa
发明人： Koji Asami , Yasuo Furukawa
IPC分类号： H03M1/06
CPC分类号： H03M1/109 , H03M1/12
摘要： A test apparatus configured to test an N-bit (N represents an integer) A/D converter is provided. A voltage generating unit outputs a 2N-valued analog voltage to the A/D converter. A capture unit captures an output code of the A/D converter for each level. A signal processing unit compares the output code captured for each level with the corresponding expected value code, corrects the value of the analog voltage for each level based upon the comparison result, and outputs the corrected analog voltage to the voltage generating unit.
摘要翻译：提供了一种被配置为测试N位（N表示整数）A / D转换器的测试装置。电压产生单元向A / D转换器输出2N值的模拟电压。捕获单元捕获每个级别的A / D转换器的输出代码。信号处理单元将每个级别捕获的输出代码与相应的预期值代码进行比较，根据比较结果对每个级别的模拟电压值进行校正，并将校正的模拟电压输出到电压产生单元。

6. 发明授权

US07859288B2 Test apparatus and test method for testing a device based on quiescent current 有权
标题翻译：基于静态电流测试器件的测试仪器和测试方法
公开(公告)号：US07859288B2
公开(公告)日：2010-12-28
申请号：US12209213
申请日：2008-09-12
申请人： Yasuo Furukawa
发明人： Yasuo Furukawa
IPC分类号： G01R31/26
CPC分类号： G01R31/31924 , G01R31/3004
摘要： Provided is A test apparatus that tests a device under test, including a power supply section that supplies power to a power supply terminal of the device under test; a power supply control section that controls the power supply section to output the power at a plurality of voltage levels; a current measuring section that measures, at each voltage level, a current value of a quiescent current of the device under test, the quiescent current being supplied to the power supply terminal of the device under test by the power supply section; and an analyzing section that analyzes whether a defect is present in the device under test by using at least three current values from among the current values measured by the current measuring section at the plurality of voltage levels.
摘要翻译：提供了一种测试被测设备的测试设备，包括向被测设备的电源端子供电的电源部分; 电源控制部分，其控制所述电源部分以多个电压电平输出电力; 电流测量部分，在每个电压电平下测量被测器件的静态电流的当前值，所述静态电流由所述电源部分提供给被测器件的电源端子; 以及分析部，其通过使用在所述多个电压电平下由所述电流测量部测量的所述电流值中的至少三个电流值来分析所述被测器件中是否存在缺陷。

7. 发明申请

US20080157804A1 CARRIER MODULE FOR ADAPTING NON-STANDARD INSTRUMENT CARDS TO TEST SYSTEMS 审中-公开
标题翻译：用于将非标准仪器卡适用于测试系统的载体模块
公开(公告)号：US20080157804A1
公开(公告)日：2008-07-03
申请号：US12048952
申请日：2008-03-14
申请人： Eric B. KUSHNICK , Yasuo Furukawa , Lawrence Kraus , James Getchell
发明人： Eric B. KUSHNICK , Yasuo Furukawa , Lawrence Kraus , James Getchell
IPC分类号： G01R1/20
CPC分类号： G01R31/31907
摘要： A carrier module that is able to adapt non-standard instrument cards to the architecture of a test system is disclosed. Instrument cards based on non-standard architectures may be combined on a single carrier module. The carrier module is then plugged into the test head of the test system. The carrier module provides circuitry, contained on a plug-in sub-module called an Application Interface Adapter (AIA), to interface between the instrument cards and the test head interface connector. Additionally, the AIA may also provide access from the instrument cards to ATE system calibration circuitry. The carrier module uses the standard data bus of the test system for housekeeping and control functions. A second bus provides the bus for the non-standard instrument cards. Software drivers provided with the instrument cards are encapsulated with an appropriate wrapper so that the cards run seamlessly in the software environment of the test system.
摘要翻译：公开了能够将非标准仪表卡适配到测试系统架构的载体模块。基于非标准架构的仪表卡可以组合在单个载体模块上。载体模块然后插入测试系统的测试头。载体模块提供包含在称为应用接口适配器（AIA）的插件子模块上的电路，用于在仪表卡和测试头接口连接器之间进行接口。此外，AIA还可以提供从仪表卡到ATE系统校准电路的访问。运营商模块使用测试系统的标准数据总线进行管理和控制功能。第二辆公交车为非标准仪表卡提供总线。仪器卡随附的软件驱动程序用适当的包装纸封装，以便卡片在测试系统的软件环境中无缝运行。

8. 发明授权

US07242197B2 Current measuring apparatus, test apparatus, and coaxial cable and assembled cable for the apparatuses 失效
标题翻译：电流测量仪器，测试仪器，同轴电缆和装置的组装电缆
公开(公告)号：US07242197B2
公开(公告)日：2007-07-10
申请号：US11385247
申请日：2006-03-21
申请人： Mitsunori Satou , Yasuo Furukawa
发明人： Mitsunori Satou , Yasuo Furukawa
IPC分类号： G01R31/08 , G01R27/08
CPC分类号： G01R15/183 , G01R1/18 , G01R15/185
摘要： There is provided a current measuring apparatus for measuring current-under-measurement flowing between a first measuring terminal and a second measuring terminal, having a plurality of primary coils whose one end is electrically connected with the first measuring terminal and another end thereof is electrically connected with the second measuring terminal, a secondary coil that generates voltage representing the current-under-measurement corresponding to the current-under-measurement flowing through the plurality of primary coils and coaxial cables, each corresponding to the plurality of primary coils and having a signal line that connects one end of the primary coil with the first measuring terminal and a shield, and the coaxial cable has the signal line, an insulating layer for coating the signal line, first one of the shield having a tape-like conductor wound around the insulating layer and second one of the shield made of a conductor provided around the first shield.
摘要翻译：提供了一种用于测量在第一测量端子和第二测量端子之间流动的电流测量装置，具有多个初级线圈，其一端与第一测量端子电连接，另一端电连接第二测量端子产生次级线圈，该次级线圈产生代表流过多个初级线圈和同轴电缆的电流下测量相应的电流下测量的电压，每个初级线圈和同轴电缆对应于多个初级线圈并且具有信号将一次线圈的一端与第一测量端子和屏蔽连接的线路，并且同轴电缆具有信号线，用于涂覆信号线的绝缘层，屏蔽体中的第一个具有卷绕在其上的带状导体绝缘层和由设置在第一屏蔽件周围的导体制成的第二屏蔽层。

9. 发明授权

US07126367B2 Test apparatus, test method, electronic device, and electronic device manufacturing method 有权
标题翻译：测试装置，测试方法，电子设备和电子设备制造方法
公开(公告)号：US07126367B2
公开(公告)日：2006-10-24
申请号：US11006868
申请日：2004-12-08
申请人： Yasuo Furukawa
发明人： Yasuo Furukawa
IPC分类号： G01R31/26 , G01R31/28
CPC分类号： G01R31/3008
摘要： A test apparatus for testing an electronic device provided with a field effect transistor, which operates in response to a given test pattern, is provided, wherein the test apparatus includes a power supply for providing electric power which drives the electronic device, a pattern generating unit for generating a plurality of test patterns sequentially and providing the electronic device with the test patterns, a leak current detecting unit for detecting a leak current of the field effect transistor, a voltage control unit for controlling a substrate voltage applied to a substrate on which the field effect transistor is provided, in order to maintain the leak current detected by the leak current detecting unit at a predetermined value, and a power supply current measuring unit for measuring a power supply current input to the electronic device at every time when each of the test patterns is applied and deciding acceptability of the electronic device on the basis of the measured power supply currents.
摘要翻译：本发明提供了一种用于测试具有响应于给定测试图案操作的场效应晶体管的电子设备的测试设备，其中测试设备包括用于提供驱动电子设备的电力的电源，模式产生单元用于顺序地产生多个测试图案并为电子设备提供测试图案;漏电流检测单元，用于检测场效应晶体管的漏电流;电压控制单元，用于控制施加到基板上的基板电压，提供场效应晶体管，以便将由漏电流检测单元检测到的漏电流保持在预定值;以及电源电流测量单元，用于在每次的每个时刻测量输入到电子设备的电源电流应用测试模式，并根据测量的功率决定电子设备的可接受性充足的电流。

10. 发明申请

US20060114015A1 Test apparatus and test method 有权
标题翻译：试验装置及试验方法
公开(公告)号：US20060114015A1
公开(公告)日：2006-06-01
申请号：US11331815
申请日：2006-01-13
申请人： Yasuo Furukawa
发明人： Yasuo Furukawa
IPC分类号： G01R31/26
CPC分类号： G01R31/31928
摘要： A test apparatus for testing switching speed of a circuit, which includes a pre-stage logic element outputting a first or second level voltage and a post-stage logic element to which the output signal of the pre-stage logic element is input, is provided, wherein the post-stage logic element includes the post-stage FET, a gate terminal of which the output signal is input to, for outputting a different level of voltage according to the case that the output signal voltage is higher or lower than a predetermined threshold voltage, and the test apparatus includes a threshold voltage setting unit for setting a threshold voltage of a post-stage field effect transistor (FET) to be different from that in a normal operation by setting a substrate voltage of the post-stage FET to have a value different from that in the normal operation of the circuit; a delay time measuring unit for measuring a delay time of the circuit to which the threshold voltage different from that in the normal operation is set; and an error detecting unit for detecting an error in switching speed of the circuit based on the delay time.
摘要翻译：提供一种用于测试电路的切换速度的测试装置，其包括输出第一或第二电平电压的前级逻辑元件和输入前级逻辑元件的输出信号的后级逻辑元件，其中后级逻辑元件包括后级FET，其输出信号被输入的栅极端子，用于根据输出信号电压高于或低于预定值的情况输出不同电平电平阈值电压，并且测试装置包括阈值电压设置单元，用于通过将后级FET的衬底电压设置为与正常操作中的阈值电压不同的阈值电压来设置具有与电路的正常工作不同的值; 用于测量与正常操作不同的阈值电压的电路的延迟时间的延迟时间测量单元; 以及误差检测单元，用于基于延迟时间检测电路的切换速度的误差。

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