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1. 发明申请

US20100281483A1 PROGRAMMABLE SCHEDULING CO-PROCESSOR 审中-公开
标题翻译：可编程调度协同处理器
公开(公告)号：US20100281483A1
公开(公告)日：2010-11-04
申请号：US12433824
申请日：2009-04-30
申请人： Shlomo Selim Rakib , Alexander Hubris , Muhammad Ahmed
发明人： Shlomo Selim Rakib , Alexander Hubris , Muhammad Ahmed
IPC分类号： G06F9/46 , G06F12/00
CPC分类号： G06F9/4881 , G06F9/30032 , G06F9/3009 , G06F9/30181 , G06F9/3828 , G06F9/3851 , G06F9/3853 , G06F9/3887 , G06F9/5066 , G06F15/8023 , G06F2209/483
摘要： A scheduling co-processor for scheduling the execution of threads on a processor is disclosed. In certain embodiments, the scheduling co-processor includes one or more engines (such as lookup tables) that are programmable with a Petri-net representation of a thread scheduling algorithm. The scheduling co-processor may further include a token list to store tokens associated with the Petri-net; an enabled-thread list to indicate which threads are enabled for execution in response to particular tokens being present in the token list; and a ready-thread list to indicate which threads from the enabled-thread list are ready for execution when data and/or space availability conditions associated with the threads are satisfied.
摘要翻译：公开了一种用于调度处理器上的线程执行的调度协处理器。在某些实施例中，调度协处理器包括可以用线程调度算法的Petri网表示来编程的一个或多个引擎（诸如查找表）。调度协处理器还可以包括用于存储与Petri网相关联的令牌的令牌列表; 启用线程列表，以指示响应于令牌列表中存在的特定令牌而启用执行的线程; 以及准备线程列表，以指示当与线程相关联的数据和/或空间可用性条件得到满足时，来自启用线程列表的哪些线程准备好执行。

2. 发明授权

US06848036B1 Method and apparatus for faster block size calculations for interleaving 有权
标题翻译：用于更快的块大小计算用于交织的方法和装置
公开(公告)号：US06848036B1
公开(公告)日：2005-01-25
申请号：US09648278
申请日：2000-08-23
申请人： Sanjay Shashi Dave , Warangkana Tepmongkol , Alexander Hubris
发明人： Sanjay Shashi Dave , Warangkana Tepmongkol , Alexander Hubris
IPC分类号： G06F12/00 , H03M13/27
CPC分类号： H03M13/2703
摘要： An interleaver for any modem or transmitter which transmits digital data. The interleaver eliminates the iterative divide step of a first prior art method to calculate the final depth of each block and the divide followed by a multiply step of a second prior art method. This is done by calculating the minimum depth, i.e., number of rows, for each 2-D block of data using a divide step and retaining the remainder. The remainder is used to determine how many blocks get an extra row when the burst length and width of each row precludes all blocks from having the same number of rows.
摘要翻译：用于传输数字数据的任何调制解调器或发射机的交织器。交织器消除了第一现有技术方法的迭代除法步骤，以计算每个块的最终深度，然后除以第二现有技术方法的乘法步骤。这是通过使用除法步骤计算每个2-D数据块的最小深度，即行数，并保留余数来完成的。剩余部分用于确定当每行的突发长度和宽度阻止所有块具有相同行数时，有多少块获得额外的行。

3. 发明授权

US09329948B2 Measuring cell damage for wear leveling in a non-volatile memory 有权
标题翻译：在非易失性存储器中测量电容器损坏
公开(公告)号：US09329948B2
公开(公告)日：2016-05-03
申请号：US13620982
申请日：2012-09-15
申请人： Yan Li , Alexander Hubris , Hao Zhong
发明人： Yan Li , Alexander Hubris , Hao Zhong
IPC分类号： G11C29/00 , G06F11/16 , G06F12/02 , G11C16/34 , G11C29/42 , G11C29/50 , G11C29/52
CPC分类号： G06F11/1666 , G06F12/0246 , G06F2212/7211 , G11C16/3495 , G11C29/42 , G11C29/50 , G11C29/52
摘要： An NVM controller measures cell damage for wear leveling in an NVM, thus improving performance, reliability, lifetime, and/or cost of a storage sub-system, such as an SSD. In a first aspect, the controller determines that an error reading a page of NVM was caused by cell damage and/or cell leakage. The controller reprograms and immediately reads back the page, detecting that the error was caused by cell damage if an error is detected during the immediate read. In a second aspect, the cell damage is tracked by updating cell damage counters for pages and/or blocks of NVM. In a third aspect, wear leveling is performed based at least in part upon measured cell damage for pages and/or blocks of NVM.
摘要翻译： NVM控制器测量NVM中磨损均衡的单元损坏，从而提高存储子系统（如SSD）的性能，可靠性，寿命和/或成本。在第一方面，控制器确定读取NVM的页面的错误是由于单元损坏和/或单元泄漏引起的。控制器重新编程并立即读回页面，如果在立即读取期间检测到错误，则检测到错误是由单元损坏引起的。在第二方面，通过更新针对NVM的页面和/或块的单元损坏计数器跟踪单元损坏。在第三方面，至少部分地基于对NVM的页面和/或块的所测量的单元损坏来执行损耗均衡。

4. 发明授权

US06839870B2 Error-correcting code interleaver 有权
标题翻译：纠错码交织器
公开(公告)号：US06839870B2
公开(公告)日：2005-01-04
申请号：US10394937
申请日：2003-03-21
申请人： Robert J. Fanfelle , Alexander Hubris
发明人： Robert J. Fanfelle , Alexander Hubris
IPC分类号： H03M13/27 , G11C29/00 , H03M13/00
CPC分类号： H03M13/2782 , H03M13/2732 , H03M13/276
摘要： Memory may be partitioned into ever-sliding FIFOs. Each of the FIFOs may be stacked end-to-end in memory with the oldest data at the base offset and the newest at the end (or vice-virsa). Each symbol, the pointer may be incremented (modulo the set size) by an appropriate amount (typically J more than for the previous symbol). After each set, the pointers may be incremented by J more than the previous increment and the process starts over, wrapping around the memory if the end of the memory is reached. After a preset number of symbols, the process may restart from an increment of J. Alternatively, the pointers may be decremented rather than incremented. Thus, the newest symbol cannibalizes the memory position vacated by the oldest symbol in the current FIFO, causing the FIFOs to “slide”, providing for a very efficient and reliable use of memory for error-correcting code interleaving.
摘要翻译：存储器可以被划分成不间断的FIFO。 FIFO中的每一个可以端到端堆叠在存储器中，而最旧的数据在基本偏移处是最新的，而最后一个在最后（或反之亦然）。每个符号，指针可以递增（模数设置大小）适当的量（通常比前一个符号多一个J）。在每个集合之后，指针可以比先前的增量增加J，并且过程重新开始，如果到达存储器的结尾，则围绕存储器缠绕。在预设数量的符号之后，该过程可以从J的增量重新开始。或者，指针可以递减而不是递增。因此，最新的符号消耗了当前FIFO中最旧符号腾出的存储器位置，导致FIFO“滑动”，为存储器提供非常有效和可靠的用于纠错码交错的位置。

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