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1. 发明申请

US20060176091A1 Delay locked loop circuit 审中-公开
标题翻译：延时锁定回路电路
公开(公告)号：US20060176091A1
公开(公告)日：2006-08-10
申请号：US11289753
申请日：2005-11-30
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata , Hideki Yoshii , Yasuyuki Doi , Makoto Hattori
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata , Hideki Yoshii , Yasuyuki Doi , Makoto Hattori
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/07 , H03L7/0891 , H03L7/0895
摘要： A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.
摘要翻译：延迟元件产生延迟的时钟信号，该时钟信号以基于参考时钟信号的上升（或下降）的延迟从基于环路滤波器的输出确定的延迟量转变。信号产生电路产生根据参考时钟信号的上升和下降以及延迟的时钟信号的转变而互补地变化的两个信号。电荷泵电路根据这两个信号执行环路滤波器，在从参考时钟信号的上升（或下降）延迟到延迟的时钟信号的转换的延迟期间进行推（或拉）（或推动）操作在从延迟的时钟信号的转变延伸到参考时钟信号的下降（或上升）的间隔期间。

2. 发明申请

US20080303567A1 DELAY LOCKED LOOP CIRCUIT 有权
标题翻译：延迟锁定环路
公开(公告)号：US20080303567A1
公开(公告)日：2008-12-11
申请号：US12033707
申请日：2008-02-19
申请人： Shiro SAKIYAMA , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata , Hideki Yoshii , Yasuyuki Doi , Makoto Hattori
发明人： Shiro SAKIYAMA , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata , Hideki Yoshii , Yasuyuki Doi , Makoto Hattori
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/07 , H03L7/0891 , H03L7/0895
摘要： A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.
摘要翻译：延迟元件产生延迟的时钟信号，该时钟信号以基于参考时钟信号的上升（或下降）的延迟从基于环路滤波器的输出确定的延迟量转变。信号产生电路产生根据参考时钟信号的上升和下降以及延迟的时钟信号的转变而互补地变化的两个信号。电荷泵电路根据这两个信号执行环路滤波器，在从参考时钟信号的上升（或下降）延迟到延迟的时钟信号的转换的延迟期间进行推（或拉）（或推动）操作在从延迟的时钟信号的转变延伸到参考时钟信号的下降（或上升）的间隔期间。

3. 发明授权

US07705645B2 Delay locked loop circuit 有权
标题翻译：延时锁定回路电路
公开(公告)号：US07705645B2
公开(公告)日：2010-04-27
申请号：US12033707
申请日：2008-02-19
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata , Hideki Yoshii , Yasuyuki Doi , Makoto Hattori
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata , Hideki Yoshii , Yasuyuki Doi , Makoto Hattori
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/07 , H03L7/0891 , H03L7/0895
摘要： A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.
摘要翻译：延迟元件产生延迟的时钟信号，该时钟信号以基于参考时钟信号的上升（或下降）的延迟从基于环路滤波器的输出确定的延迟量转变。信号产生电路产生根据参考时钟信号的上升和下降以及延迟的时钟信号的转变而互补地变化的两个信号。电荷泵电路根据这两个信号执行环路滤波器，在从参考时钟信号的上升（或下降）延迟到延迟的时钟信号的转换的延迟期间进行推（或拉）（或推动）操作在从延迟的时钟信号的转变延迟到参考时钟信号的下降（或上升）的间隔期间。

4. 发明授权

US07388405B2 Signal transmission circuit 失效
标题翻译：信号传输电路
公开(公告)号：US07388405B2
公开(公告)日：2008-06-17
申请号：US11513239
申请日：2006-08-31
申请人： Yusuke Tokunaga , Shiro Sakiyama , Shiro Dosho , Yasuyuki Doi , Makoto Hattori
发明人： Yusuke Tokunaga , Shiro Sakiyama , Shiro Dosho , Yasuyuki Doi , Makoto Hattori
IPC分类号： H03K19/094 , H03K19/0175 , H03B1/00
CPC分类号： H03K19/018571 , H03F1/0261 , H03F3/505 , H03F2200/18 , H04L25/028
摘要： A time required for an output voltage of a source follower to rise from Low to a predetermined voltage depends on a bias voltage. Therefore, by setting a converged voltage of an output voltage to be high by increasing the bias voltage, the time required to rise up to the predetermined voltage can be reduced. Therefore, a first source follower which is biased so that the converged value of the output voltage becomes a predetermined Hi voltage when an input data signal goes from Low to Hi, and a second source follower which is biased so as to become the Hi voltage after a period of one clock when an input data signal goes from Low to Hi, are used. The two source followers are operated with appropriate timing.
摘要翻译：源极跟随器的输出电压从低电平上升到预定电压所需的时间取决于偏置电压。因此，通过增加偏置电压来设定输出电压的收敛电压为高，可以降低上升到预定电压所需的时间。因此，当输入数据信号从低电平变为高电平时，被偏压使得输出电压的会聚值变为预定的Hi电压的第一源极跟随器，以及被偏置以便成为Hi电压之后的第二源极跟随器使用输入数据信号从低电平变为高电平时的一个时钟周期。两个来源追随者在适当的时机运行。

5. 发明申请

US20070090859A1 Signal transmission circuit 失效
标题翻译：信号传输电路
公开(公告)号：US20070090859A1
公开(公告)日：2007-04-26
申请号：US11513239
申请日：2006-08-31
申请人： Yusuke Tokunaga , Shiro Sakiyama , Shiro Dosho , Yasuyuki Doi , Makoto Hattori
发明人： Yusuke Tokunaga , Shiro Sakiyama , Shiro Dosho , Yasuyuki Doi , Makoto Hattori
IPC分类号： H03K19/094
CPC分类号： H03K19/018571 , H03F1/0261 , H03F3/505 , H03F2200/18 , H04L25/028
摘要： A time required for an output voltage of a source follower to rise from Low to a predetermined voltage depends on a bias voltage. Therefore, by setting a converged voltage of an output voltage to be high by increasing the bias voltage, the time required to rise up to the predetermined voltage can be reduced. Therefore, a first source follower which is biased so that the converged value of the output voltage becomes a predetermined Hi voltage when an input data signal goes from Low to Hi, and a second source follower which is biased so as to become the Hi voltage after a period of one clock when an input data signal goes from Low to Hi, are used. The two source followers are operated with appropriate timing.
摘要翻译：源极跟随器的输出电压从低电平上升到预定电压所需的时间取决于偏置电压。因此，通过增加偏置电压来设定输出电压的收敛电压为高，可以降低上升到预定电压所需的时间。因此，当输入数据信号从低电平变为高电平时，被偏压使得输出电压的会聚值变为预定的Hi电压的第一源极跟随器，以及被偏置以便成为Hi电压之后的第二源极跟随器使用输入数据信号从低电平变为高电平时的一个时钟周期。两个来源追随者在适当的时机运行。

6. 发明申请

US20070146231A1 Display drive device, display signal transfer device, and display device 审中-公开
标题翻译：显示驱动装置，显示信号传送装置和显示装置
公开(公告)号：US20070146231A1
公开(公告)日：2007-06-28
申请号：US11641875
申请日：2006-12-20
申请人： Yoshihisa Hamahashi , Yasuyuki Doi , Tooru Suyama , Makoto Hattori , Tomoya Ishikawa
发明人： Yoshihisa Hamahashi , Yasuyuki Doi , Tooru Suyama , Makoto Hattori , Tomoya Ishikawa
IPC分类号： G09G5/00
CPC分类号： G09G3/3688 , G09G2310/027 , G09G2320/0223 , G09G2330/021 , G09G2330/028 , G09G2370/08
摘要： A receiving circuit receives one or plural first signals involving display from the outside through an input unit. A first transmitting circuit transmits one or plural second signals relevant to the first signal from the first output unit. A second transmitting circuit transmits the second signal from the second output unit.
摘要翻译：接收电路通过输入单元从外部接收涉及显示的一个或多个第一信号。第一发送电路从第一输出单元发送与第一信号相关的一个或多个第二信号。第二发送电路从第二输出单元发送第二信号。

7. 发明申请

US20080158033A1 DRIVING DEVICE FOR IMAGE DISPLAY SYSTEM 审中-公开
标题翻译：用于图像显示系统的驱动装置
公开(公告)号：US20080158033A1
公开(公告)日：2008-07-03
申请号：US11965279
申请日：2007-12-27
申请人： Yasuyuki Doi , Makoto Hattori , Hisao Kunitani , Atsuhisa Kageyama , Tetsuro Oomori , Osamu Sarai , Tooru Suyama , Kurumi Nakayama , Kazuya Matsumoto
发明人： Yasuyuki Doi , Makoto Hattori , Hisao Kunitani , Atsuhisa Kageyama , Tetsuro Oomori , Osamu Sarai , Tooru Suyama , Kurumi Nakayama , Kazuya Matsumoto
IPC分类号： G09G3/36
CPC分类号： G09G3/3685 , G09G3/2059 , G09G3/3696 , G09G2310/027 , G09G2340/0428
摘要： A driving device for driving an image display system, which sequentially receives input image data corresponding to gradation of each pixel of a display image and outputs a driving voltage signal includes: an operation section for obtaining output image data of which a bit number is smaller than a bit number of the input image data based on input image data of a target pixel to be processed and input image data of a pixel in vicinity of the target pixel; a reference voltage generation section for generating a plurality of reference voltages of different levels; and a reference voltage selection section for selecting one of the plurality of reference voltages. The operation section is configured to obtain output image data of the target pixel so that a difference between the input image data and output image data of the target pixel and a difference between the input image data and output image data of the pixel in vicinity of the target pixel cancel out each other.
摘要翻译：一种用于驱动图像显示系统的驱动装置，其顺序地接收与显示图像的每个像素的灰度对应的输入图像数据并输出驱动电压信号，包括：操作部，用于获得位数小于基于要处理的目标像素的输入图像数据的输入图像数据的位数，并输入目标像素附近的像素的图像数据; 用于产生不同电平的多个参考电压的参考电压产生部分; 以及用于选择多个参考电压中的一个的参考电压选择部分。操作部被配置为获得目标像素的输出图像数据，使得输入图像数据和目标像素的输出图像数据之间的差异以及输入图像数据与输入图像数据之间的像素的输出图像数据之间的差异目标像素相互抵消。

8. 发明授权

US07671775B2 Digital-to-analog converter 失效
标题翻译：数模转换器
公开(公告)号：US07671775B2
公开(公告)日：2010-03-02
申请号：US12236038
申请日：2008-09-23
申请人： Yasuyuki Doi , Kurumi Nakayama , Makoto Hattori , Hideki Ikeda
发明人： Yasuyuki Doi , Kurumi Nakayama , Makoto Hattori , Hideki Ikeda
IPC分类号： H03M1/66
CPC分类号： H03M1/682 , G09G3/3688 , G09G3/3696 , G09G2310/027 , H03M1/76 , H03M1/765
摘要： A converter of 6-bit input includes a reference voltage generating circuit generating 17 reference voltages, a first switch circuit having 19 switch pairs each including MOS transistors for selecting two adjacent reference voltages in accordance with the four most significant bits, a second switch circuit including a series circuit of MOS transistors for dividing the selected two reference voltages into four to obtain three intermediate voltages, and a third switch circuit for selectively outputting the lower of the selected two reference voltages or one of the three intermediate voltages. In a second mode in which a gray level having a smaller ON-resistance of a MOS transistor than that in the first mode is selected, the number of MOS transistors used in the first and second switch circuits for voltage division is increased.
摘要翻译： 6位输入的转换器包括产生17个参考电压的参考电压产生电路，具有19个开关对的第一开关电路，每个开关对包括用于根据四个最高有效位选择两个相邻参考电压的MOS晶体管;第二开关电路，包括用于将所选择的两个参考电压分为四个以获得三个中间电压的MOS晶体管的串联电路;以及用于选择性地输出所选择的两个参考电压中的较低者或三个中间电压中的一个的第三开关电路。在选择具有比第一模式中的MOS晶体管的导通电阻小的灰度级的第二模式中，用于分压的第一和第二开关电路中使用的MOS晶体管的数量增加。

9. 发明申请

US20090184856A1 DIGITAL-TO-ANALOG CONVERTER 失效
标题翻译：数字到模拟转换器
公开(公告)号：US20090184856A1
公开(公告)日：2009-07-23
申请号：US12236038
申请日：2008-09-23
申请人： Yasuyuki DOI , Kurumi Nakayama , Makoto Hattori , Hideki Ikeda
发明人： Yasuyuki DOI , Kurumi Nakayama , Makoto Hattori , Hideki Ikeda
IPC分类号： H03M1/78
CPC分类号： H03M1/682 , G09G3/3688 , G09G3/3696 , G09G2310/027 , H03M1/76 , H03M1/765
摘要： A converter of 6-bit input includes a reference voltage generating circuit generating 17 reference voltages, a first switch circuit having 19 switch pairs each including MOS transistors for selecting two adjacent reference voltages in accordance with the four most significant bits, a second switch circuit including a series circuit of MOS transistors for dividing the selected two reference voltages into four to obtain three intermediate voltages, and a third switch circuit for selectively outputting the lower of the selected two reference voltages or one of the three intermediate voltages. In a second mode in which a gray level having a smaller ON-resistance of a MOS transistor than that in the first mode is selected, the number of MOS transistors used in the first and second switch circuits for voltage division is increased.
摘要翻译： 6位输入的转换器包括产生17个参考电压的参考电压产生电路，具有19个开关对的第一开关电路，每个开关对包括用于根据四个最高有效位选择两个相邻参考电压的MOS晶体管;第二开关电路，包括用于将所选择的两个参考电压分为四个以获得三个中间电压的MOS晶体管的串联电路;以及用于选择性地输出所选择的两个参考电压中的较低者或三个中间电压中的一个的第三开关电路。在选择具有比第一模式中的MOS晶体管的导通电阻小的灰度级的第二模式中，用于分压的第一和第二开关电路中使用的MOS晶体管的数量增加。

10. 发明授权

US08952766B2 Control board, inverter device and integrated-inverter electric compressor 有权
标题翻译：控制板，变频器和集成逆变电动压缩机
公开(公告)号：US08952766B2
公开(公告)日：2015-02-10
申请号：US13386287
申请日：2010-12-20
申请人： Makoto Hattori , Masahiko Asai
发明人： Makoto Hattori , Masahiko Asai
IPC分类号： H02K11/02 , H02M7/00 , H03H1/00 , H02K11/00
CPC分类号： H02K11/0073 , H02K11/33 , H02M1/44 , H02M7/003 , H03H1/0007 , H05K1/0231 , H05K1/0262 , H05K2201/09972 , H05K2201/10015
摘要： An object is to provide a control board, an inverter device, and an integrated-inverter electric compressor that are capable of improving electromagnetic compatibility (EMC property) and improving reliability against input/output of electromagnetic noise, which shows a tendency towards greater complexity and intensity. A control board to which two power systems, that is, a low-voltage power system and a high-voltage power system, are inputs, comprising a low-voltage circuit and a high-voltage circuit, and a low-voltage-side ground region and a high-voltage-side ground region that are formed in correspondence with the circuits, respectively, wherein frame ground regions are provided at a plurality of positions on the control board, and a plurality of communication line patterns connected to the low-voltage circuit are respectively connected to both the low-voltage-side ground region and the frame ground region through capacitance elements with various capacitances.
摘要翻译：本发明的目的是提供一种能够提高电磁兼容性（EMC性能）并且提高电磁噪声的输入/输出的可靠性的控制板，逆变器装置和集成逆变电动压缩机，其显示出更大复杂性的趋势，强度。两个电力系统，即低压电力系统和高压电力系统的控制板是输入，包括低压电路和高压电路以及低压侧接地区域和与电路对应地形成的高压侧接地区域，其中在接地控制板上的多个位置设置有帧接地区域，以及多个与低电压连接的通信线路图形电路分别通过具有各种电容的电容元件连接到低电压侧接地区域和框架接地区域两者。

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