会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 7. 发明授权
    • Low-power area-efficient absolute value arithmetic unit
    • 低功率面积效率绝对值运算单元
    • US5251164A
    • 1993-10-05
    • US887511
    • 1992-05-22
    • Jeffrey M. DodsonChristopher T. Cheng
    • Jeffrey M. DodsonChristopher T. Cheng
    • G06F7/50G06F7/38G06F7/483G06F7/506G06F7/508G06F7/544
    • G06F7/544G06F2207/5442G06F7/508
    • A high-speed, area efficient, low-power absolute value arithmetic unit that efficiently produces the absolute value of the difference of two input operands. This arithmetic unit is adaptable to provide other output functions. Further, the arithmetic unit of the present invention may be utilized as a data path element in a high performance floating point arithmetic unit. The present invention includes a propagate and generate block, a carry-chain-and a difference multiplexer. Operands A and B are received by the absolute value arithmetic unit. The propagate and generate block converts operands A and B into propagate signals and generate signals. The carry-chain-receives propagate and generate signals and produces carry-chain-propagate signals and carry-chain-generate signals for every bit, where the most significant carry-chain-generate signal is used to indicate a borrow. The difference multiplexer receives the carry-chain-propagate and carry-chain-generate signals as well as propagate singals from the propagate-and-generate block and produces A-B and B-A. The difference multiplexer then selects either A-B or B-A to produce as an output the absolute value of A-B. The borrow signal acts as the selection means for obtaining the absolute value of A-B. In either case, .vertline.A-B.vertline. is obtained with essentially the same amount of hardware as only one core subtractor. The present invention uses approximately half the amount of hardware as the fastest conventional absolute value arithmetic units and therefore is approximately 50% more compact. The entire absolute value arithmetic unit of the present invention requires essentially the same amount of area as only one conventional adder/subtractor. In addition, the present invention sacrifices no speed to achieve its smaller size and consumes less power than a conventional absolute value subtractor.
    • 高效,区域有效的低功率绝对值算术单元,有效地产生两个输入操作数差的绝对值。 该算术单元适用于提供其他输出功能。 此外,本发明的算术单元可以用作高性能浮点运算单元中的数据路径元素。 本发明包括传播和生成块,进位链和差异多路复用器。 操作数A和B由绝对值运算单元接收。 传播和生成块将操作数A和B转换成传播信号并产生信号。 进位链接收传播并产生信号,并产生进位链传播信号,并为每个位携带链生成信号,其中最重要的进位链生成信号用于指示借位。 差分多路复用器接收携带链传播和携带链生成信号以及从传播和生成块传播信号,并产生A-B和B-A。 差分复用器然后选择A-B或B-A以产生A-B的绝对值作为输出。 借用信号用作获得A-B的绝对值的选择装置。 在任何一种情况下,| A-B |的获取与基本上相同的硬件数量只有一个核心减法器。 本发明使用大约一半的硬件作为最快的常规绝对值运算单元,因此大约50%更紧凑。 本发明的整个绝对值运算单元仅需要与一个常规的加法器/减法器基本相同的面积。 此外,本发明与传统的绝对值​​减法器相比,不牺牲速度来实现其更小的尺寸和更少的功率消耗。