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1. 发明授权

US08502373B2 3-D integrated circuit lateral heat dissipation 有权
标题翻译： 3-D集成电路横向散热
公开(公告)号：US08502373B2
公开(公告)日：2013-08-06
申请号：US12115076
申请日：2008-05-05
申请人： Kenneth Kaskoun , Shiqun Gu , Matthew Nowak
发明人： Kenneth Kaskoun , Shiqun Gu , Matthew Nowak
IPC分类号： H01L23/34
CPC分类号： H01L25/0657 , H01L23/3677 , H01L23/3732 , H01L23/3735 , H01L2224/16145 , H01L2225/06513 , H01L2225/06589 , H01L2924/01019
摘要： By filling an air gap between tiers of a stacked IC device with a thermally conductive material, heat generated at one or more locations within one of the tiers can be laterally displaced. The lateral displacement of the heat can be along the full length of the tier and the thermal material can be electrically insulating. Through silicon-vias (TSVs) can be constructed at certain locations to assist in heat dissipation away from thermally troubled locations.
摘要翻译：通过在层叠的IC器件的层之间填充导热材料，在一个层内的一个或多个位置处产生的热可以横向移位。热的横向位移可以沿着层的整个长度，并且热材料可以是电绝缘的。通过硅通孔（TSV）可以在某些位置构建，以帮助散热的位置。

2. 发明申请

US20120061804A1 Systems and Methods for Enabling Esd Protection on 3-D Stacked Devices 有权
标题翻译：在3-D堆叠设备上启用Esd保护的系统和方法
公开(公告)号：US20120061804A1
公开(公告)日：2012-03-15
申请号：US13298884
申请日：2011-11-17
申请人： Kenneth Kaskoun , Shiqun Gu , Matthew Nowak
发明人： Kenneth Kaskoun , Shiqun Gu , Matthew Nowak
IPC分类号： H01L25/065 , H01L21/98
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/60 , H01L24/06 , H01L24/16 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/13099 , H01L2224/14181 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01027 , H01L2924/01033 , H01L2924/01093 , H01L2924/10253 , H01L2924/14 , H01L2924/00 , H01L2224/05552
摘要： An electrostatic discharge (ESD) protection device is fabricated in a vertical space between active layers of stacked semiconductor dies thereby utilizing space that would otherwise be used only for communication purposes. The vertical surface area of the through silicon vias (TSVs) is used for absorbing large voltages resulting from ESD events. In one embodiment, an ESD diode is created in a vertical TSV between active layers of the semiconductor dies of a stacked device. This ESD diode can be shared by circuitry on both semiconductor dies of the stack thereby saving space and reducing die area required by ESD protection circuitry.
摘要翻译：在堆叠的半导体管芯的有源层之间的垂直空间中制造静电放电（ESD）保护装置，从而利用否则将仅用于通信目的的空间。通过硅通孔（TSV）的垂直表面积用于吸收由ESD事件引起的大电压。在一个实施例中，在层叠器件的半导体管芯的有源层之间的垂直TSV中产生ESD二极管。该ESD二极管可以由堆叠的两个半导体管芯上的电路共享，从而节省了ESD保护电路所需的空间和减小管芯面积。

3. 发明授权

US08125040B2 Two mask MTJ integration for STT MRAM 有权
标题翻译：两个掩模MTJ集成为STT MRAM
公开(公告)号：US08125040B2
公开(公告)日：2012-02-28
申请号：US12405461
申请日：2009-03-17
申请人： Seung H. Kang , Xia Li , Shiqun Gu , Matthew Nowak
发明人： Seung H. Kang , Xia Li , Shiqun Gu , Matthew Nowak
IPC分类号： H01L29/82
CPC分类号： H01L43/08 , G11C11/161 , H01L43/12
摘要： A method for forming a magnetic tunnel junction (MTJ) for magnetic random access memory (MRAM) using two masks includes depositing over an interlevel dielectric layer containing an exposed first interconnect metallization, a first electrode, a fixed magnetization layer, a tunneling barrier layer, a free magnetization layer and a second electrode. An MTJ structure including the tunnel barrier layer, free layer and second electrode is defined above the first interconnect metallization by a first mask. A first passivation layer encapsulates the MTJ structure, leaving the second electrode exposed. A third electrode is deposited in contact with the second electrode. A second mask is used to pattern a larger structure including the third electrode, the first passivation layer, the fixed magnetization layer and the first electrode. A second dielectric passivation layer covers the etched plurality of layers, the first interlevel dielectric layer and the first interconnect metallization.
摘要翻译：使用两个掩模形成用于磁性随机存取存储器（MRAM）的磁性隧道结（MTJ）的方法包括在包含暴露的第一互连金属化的层间介质层上沉积，第一电极，固定磁化层，隧道势垒层，自由磁化层和第二电极。包括隧道势垒层，自由层和第二电极的MTJ结构通过第一掩模限定在第一互连金属化之上。第一钝化层封装MTJ结构，留下第二电极。沉积与第二电极接触的第三电极。使用第二掩模来图案化包括第三电极，第一钝化层，固定磁化层和第一电极的较大结构。第二电介质钝化层覆盖被蚀刻的多个层，第一层间介质层和第一互连金属化层。

4. 发明申请

US20120001297A1 Techniques for Placement of Active and Passive Devices within a Chip 有权
标题翻译：主动和被动设备放置在芯片内的技术
公开(公告)号：US20120001297A1
公开(公告)日：2012-01-05
申请号：US13231084
申请日：2011-09-13
申请人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Matthew Nowak
发明人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Matthew Nowak
IPC分类号： H01L27/06
CPC分类号： H01L27/0617 , H01L23/481 , H01L23/5223 , H01L23/5227 , H01L27/0688 , H01L28/10 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs).
摘要翻译：半导体管芯包括具有第一和第二侧面的半导体衬底层，与半导体衬底层的第二侧相邻的金属层，在半导体衬底层的第一侧上的有源层中的一个或多个有源器件; 以及与有源层电连通的金属层中的无源器件。无源器件可以通过硅通孔（TSV）电耦合到有源层。

5. 发明授权

US08080862B2 Systems and methods for enabling ESD protection on 3-D stacked devices 有权
标题翻译：用于在3-D堆叠器件上实现ESD保护的系统和方法
公开(公告)号：US08080862B2
公开(公告)日：2011-12-20
申请号：US12206914
申请日：2008-09-09
申请人： Kenneth Kaskoun , Shiqun Gu , Matthew Nowak
发明人： Kenneth Kaskoun , Shiqun Gu , Matthew Nowak
IPC分类号： H01L23/58
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/60 , H01L24/06 , H01L24/16 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/13099 , H01L2224/14181 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01027 , H01L2924/01033 , H01L2924/01093 , H01L2924/10253 , H01L2924/14 , H01L2924/00 , H01L2224/05552
摘要： An electrostatic discharge (ESD) protection device is fabricated in a vertical space between active layers of stacked semiconductor dies thereby utilizing space that would otherwise be used only for communication purposes. The vertical surface area of the through silicon vias (TSVs) is used for absorbing large voltages resulting from ESD events. In one embodiment, an ESD diode is created in a vertical TSV between active layers of the semiconductor dies of a stacked device. This ESD diode can be shared by circuitry on both semiconductor dies of the stack thereby saving space and reducing die area required by ESD protection circuitry.
摘要翻译：在堆叠的半导体管芯的有源层之间的垂直空间中制造静电放电（ESD）保护装置，从而利用否则将仅用于通信目的的空间。通过硅通孔（TSV）的垂直表面积用于吸收由ESD事件引起的大电压。在一个实施例中，在层叠器件的半导体管芯的有源层之间的垂直TSV中产生ESD二极管。该ESD二极管可以由堆叠的两个半导体管芯上的电路共享，从而节省了ESD保护电路所需的空间和减小管芯面积。

6. 发明授权

US08508301B2 Three dimensional inductor, transformer and radio frequency amplifier 有权
标题翻译：三维电感，变压器和射频放大器
公开(公告)号：US08508301B2
公开(公告)日：2013-08-13
申请号：US13294351
申请日：2011-11-11
申请人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Lew G. Chua-Eoan , Seyfollah S. Bazarjani , Matthew Nowak
发明人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Lew G. Chua-Eoan , Seyfollah S. Bazarjani , Matthew Nowak
IPC分类号： H03F3/14
CPC分类号： H01L28/10 , H01F17/0013 , H01F19/04 , H01F2017/002 , H01L23/481 , H01L23/5227 , H01L27/0207 , H01L2224/16145 , H01L2924/3011
摘要： A three dimensional on-chip radio frequency amplifier is disclosed that includes first and second transformers and a first transistor. The first transformer includes first and second inductively coupled inductors. The second transformer includes third and fourth inductively coupled inductors. Each inductor includes multiple first segments in a first metal layer; multiple second segments in a second metal layer; first and second inputs, and multiple through vias coupling the first and second segments to form a continuous path between the first and second inputs. The first input of the first inductor is coupled to an amplifier input; the first input of the second inductor is coupled to the first transistor gate; the first input of the third inductor is coupled to the first transistor drain, the first input of the fourth inductor is coupled to an amplifier output. The second inductor inputs and the first transistor source are coupled to ground.
摘要翻译：公开了一种三维片上射频放大器，其包括第一和第二变压器和第一晶体管。第一变压器包括第一和第二电感耦合电感器。第二变压器包括第三和第四电感耦合电感器。每个电感器包括在第一金属层中的多个第一段; 第二金属层中的多个第二段; 第一和第二输入以及耦合第一和第二段的多通孔，以形成第一和第二输入之间的连续路径。第一电感器的第一输入耦合到放大器输入端; 第二电感器的第一输入耦合到第一晶体管栅极; 第三电感器的第一输入耦合到第一晶体管漏极，第四电感器的第一输入耦合到放大器输出端。第二电感器输入和第一晶体管源耦合到地。

7. 发明申请

US20120040509A1 Techniques for Placement of Active and Passive Devices within a Chip 有权
标题翻译：主动和被动设备放置在芯片内的技术
公开(公告)号：US20120040509A1
公开(公告)日：2012-02-16
申请号：US13279570
申请日：2011-10-24
申请人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Matthew Nowak
发明人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Matthew Nowak
IPC分类号： H01L21/02
CPC分类号： H01L27/0617 , H01L23/481 , H01L23/5223 , H01L23/5227 , H01L27/0688 , H01L28/10 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing a semiconductor device includes fabricating an active layer on a first side of a semiconductor substrate. The method also includes fabricating a metal layer on a second side of the semiconductor substrate. The metal layer includes a passive device embedded within the metal layer. The passive device can electrically couple to the active layer with through vias.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底的第一侧上制造有源层。该方法还包括在半导体衬底的第二侧上制造金属层。金属层包括嵌入金属层内的无源器件。无源器件可以通过通孔电耦合到有源层。

8. 发明申请

US20110084765A1 Three Dimensional Inductor and Transformer 有权
标题翻译：三维电感和变压器
公开(公告)号：US20110084765A1
公开(公告)日：2011-04-14
申请号：US12576033
申请日：2009-10-08
申请人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Lew G. Chua-Eoan , Seyfollah S. Bazarjani , Matthew Nowak
发明人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Lew G. Chua-Eoan , Seyfollah S. Bazarjani , Matthew Nowak
IPC分类号： H03F3/16 , H01F5/00
CPC分类号： H01L28/10 , H01F17/0013 , H01F19/04 , H01F2017/002 , H01L23/481 , H01L23/5227 , H01L27/0207 , H01L2224/16145 , H01L2924/3011
摘要： A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments of a first metal layer, a plurality of segments of a second metal layer, a first inductor input, a second inductor input, and a plurality of through silicon vias coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip.
摘要翻译：公开了三维片上电感器，变压器和射频放大器。射频放大器包括一对变压器和晶体管。变压器包括至少两个电感耦合电感器。电感器包括第一金属层的多个段，第二金属层的多个段，第一电感器输入端，第二电感器输入端和耦合第一金属层的多个段的多个穿通硅通孔以及第二金属层的多个段，以在第一电感器输入端和第二电感器输入端之间形成连续的，不相交的路径。电感器可以具有对称或不对称的几何形状。第一金属层可以是芯片的后端部分中的金属层。第二金属层可以位于芯片的再分布设计层中。

9. 发明申请

US20100059869A1 Systems and Methods for Enabling ESD Protection on 3-D Stacked Devices 有权
标题翻译：在3-D堆叠器件上实现ESD保护的系统和方法
公开(公告)号：US20100059869A1
公开(公告)日：2010-03-11
申请号：US12206914
申请日：2008-09-09
申请人： Kenneth Kaskoun , Shiqun Gu , Matthew Nowak
发明人： Kenneth Kaskoun , Shiqun Gu , Matthew Nowak
IPC分类号： H01L23/52 , H01L21/50 , H02H9/04 , H01L23/538
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/60 , H01L24/06 , H01L24/16 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/13099 , H01L2224/14181 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01027 , H01L2924/01033 , H01L2924/01093 , H01L2924/10253 , H01L2924/14 , H01L2924/00 , H01L2224/05552
摘要： An electrostatic discharge (ESD) protection device is fabricated in a vertical space between active layers of stacked semiconductor dies thereby utilizing space that would otherwise be used only for communication purposes. The vertical surface area of the through silicon vias (TSVs) is used for absorbing large voltages resulting from ESD events. In one embodiment, an ESD diode is created in a vertical TSV between active layers of the semiconductor dies of a stacked device. This ESD diode can be shared by circuitry on both semiconductor dies of the stack thereby saving space and reducing die area required by ESD protection circuitry.
摘要翻译：在堆叠的半导体管芯的有源层之间的垂直空间中制造静电放电（ESD）保护装置，从而利用否则将仅用于通信目的的空间。通过硅通孔（TSV）的垂直表面积用于吸收由ESD事件引起的大电压。在一个实施例中，在层叠器件的半导体管芯的有源层之间的垂直TSV中产生ESD二极管。该ESD二极管可以由堆叠的两个半导体管芯上的电路共享，从而节省了ESD保护电路所需的空间和减小管芯面积。

10. 发明申请

US20100038801A1 Corrosion Control of Stacked Integrated Circuits 有权
标题翻译：堆叠集成电路的腐蚀控制
公开(公告)号：US20100038801A1
公开(公告)日：2010-02-18
申请号：US12192514
申请日：2008-08-15
申请人： Shiqun Gu , Matthew Nowak
发明人： Shiqun Gu , Matthew Nowak
IPC分类号： H01L23/20 , H01L21/58
CPC分类号： H01L25/0657 , H01L25/50 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/13025 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A system and method prevent corrosive elements (or at least the oxidizing agent) from making contact with metal connections at the interface between two layers of a stacked IC device. When layers are positioned in proximity to each other, a cavity is formed at the boundary of the planar surfaces of the layers. This cavity is bounded by a peripheral seal between the layers. In one embodiment, a vacuum is created within the cavity thereby reducing the corrosive atmosphere within the cavity. In another embodiment, the cavity is filled with an inert gas, such as argon. Once the cavity has oxidizing elements reduced, the peripheral seal can be encapsulated to prevent seepage of contaminants into the cavity.
摘要翻译：一种系统和方法可以防止腐蚀性元件（或至少氧化剂）在层叠IC器件的两层之间的界面处与金属连接接触。当层彼此靠近地定位时，在层的平面表面的边界处形成空腔。该空腔由层之间的周边密封界定。在一个实施例中，在空腔内产生真空，从而减小空腔内的腐蚀性气氛。在另一个实施例中，空腔填充惰性气体，例如氩气。一旦腔体的氧化元件减少，外围密封件就可以被密封，以防止污染物进入腔体中。

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