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1. 发明授权

US4922911A Electrode 失效
标题翻译：电极
公开(公告)号：US4922911A
公开(公告)日：1990-05-08
申请号：US333833
申请日：1989-04-05
申请人： Shintaro Wada , Yoichi Nomura , Hisanori Takahashi , Masayuki Konno
发明人： Shintaro Wada , Yoichi Nomura , Hisanori Takahashi , Masayuki Konno
IPC分类号： A61B5/0408 , A61B5/0416 , B32B15/08
CPC分类号： A61B5/04087 , A61B5/0416 , B32B15/08
摘要： An electrode is disclosed, comprising an electrically conductive substrate and a shrinkable layer laminated on the substrate, wherein a cut is provided on the electrode so as to form a connection terminal portion projecting outwards upon shrinkage of the shrinkable layer.
摘要翻译：公开了一种电极，其包括导电基板和层压在基板上的可收缩层，其中在电极上设置切口，以便形成在可收缩层收缩时向外突出的连接端子部分。

2. 发明授权

US4679563A Biomedical electrode 失效
标题翻译：生物医学电极
公开(公告)号：US4679563A
公开(公告)日：1987-07-14
申请号：US823175
申请日：1986-01-28
申请人： Shintaro Wada , Hisanori Takahashi , Yoichi Nomura
发明人： Shintaro Wada , Hisanori Takahashi , Yoichi Nomura
IPC分类号： A61B5/0408 , A61B5/04
CPC分类号： A61B5/04087
摘要： A biomedical electrode comprising a flexible electrode plate which conforms to the skin surface of a living body, and an electrically conductive adhesive layer which fixes the electrode plate on the skin surface and transmits an electric signal from the living body to said electrode plate, wherein a non-contact area to which said conductive adhesive layer is not substantially bonded is formed on the electrode plate and an electrically conductive tongue for connecting a terminal which takes said electric signal from the living body to a biomedical diagnostic apparatus is provided on the non-contact area by forming cut thereon.
摘要翻译：一种生物医学电极，其包括符合生物体的皮肤表面的柔性电极板和将电极板固定在皮肤表面上并将电信号从活体传递到所述电极板的导电粘合剂层，其中a 在电极板上形成有导电性粘合剂层基本上不接合的非接触区域，并且在非接触状态下设置用于将从生物体获取电信号的端子连接到生物医学诊断装置的导电舌片区域。

3. 发明授权

US4602640A Biomedical electrode 失效
标题翻译：生物医学电极
公开(公告)号：US4602640A
公开(公告)日：1986-07-29
申请号：US761282
申请日：1985-08-01
申请人： Shintaro Wada , Hisanori Takahashi , Yoichi Nomura
发明人： Shintaro Wada , Hisanori Takahashi , Yoichi Nomura
IPC分类号： A61B5/0408 , A61N1/04 , H01B1/12 , A61B5/04
CPC分类号： A61N1/0496 , H01B1/122
摘要： A biomedical electrode comprising an electrode plate and an electroconductive material prepared by polymerizing unsaturated monomer containing a phosphoric or phosphorous group.
摘要翻译：一种生物医学电极，包括电极板和通过聚合含有磷酸或磷酸基团的不饱和单体制备的导电材料。

4. 发明授权

US5266371A Adhesive dressing sheet 失效
标题翻译：胶粘剂敷料片
公开(公告)号：US5266371A
公开(公告)日：1993-11-30
申请号：US938684
申请日：1992-09-01
申请人： Tetsuji Sugii , Shintaro Wada , Masayuki Konno
发明人： Tetsuji Sugii , Shintaro Wada , Masayuki Konno
IPC分类号： A61F13/00 , A61F13/02
CPC分类号： A61F13/023 , A61F2013/00817 , A61F2013/00829 , A61F2013/00846 , A61F2013/00868 , A61F2013/00902 , Y10T428/1462 , Y10T428/15 , Y10T428/24273 , Y10T428/24322 , Y10T428/24331 , Y10T428/2495 , Y10T428/24967 , Y10T428/24975 , Y10T428/28 , Y10T428/2839 , Y10T428/2848 , Y10T428/31551
摘要： An adhesive dressing sheet is disclosed, comprising a polymer film having a high flexibility, an adhesive layer provided on one side of the polymer film, a peeling liner temporarily provided on the adhesive layer, and a flexible sheet on the other side of the polymer film, wherein a bending line is provided on the peeling liner in a direction almost at right angles to the peeling direction of the liner, and the flexible sheet has self supporting properties such that when the liner is peeled off up to the bending line and bent, the liner bending piece does not expand to an angle of 90.degree. or more.
摘要翻译：公开了一种粘合性敷料片，其包含高弹性的聚合物膜，设置在聚合物膜的一侧上的粘合层，临时设置在粘合剂层上的剥离衬垫和在聚合物膜的另一侧上的柔性片其特征在于，在与所述衬垫的剥离方向大致成直角的方向上，在所述剥离衬垫上设置弯曲线，并且所述柔性片具有自支撑性，使得当所述衬垫被剥离到所述弯曲线并弯曲时，内衬弯曲件不会膨胀到90°以上的角度。

5. 发明授权

US08423999B2 Computer system, virtual machine monitor and scheduling method for virtual machine monitor 有权
标题翻译：计算机系统，虚拟机监控和虚拟机监控调度方法
公开(公告)号：US08423999B2
公开(公告)日：2013-04-16
申请号：US12834374
申请日：2010-07-12
申请人： Shuhei Matsumoto , Hironori Inoue , Shintaro Wada
发明人： Shuhei Matsumoto , Hironori Inoue , Shintaro Wada
IPC分类号： G06F9/455 , G06F9/46
CPC分类号： G06F9/45533 , G06F9/45541 , G06F9/4881 , G06F2209/483 , Y02D10/24
摘要： In a computer system according to the background art, when a request to halt a virtual processor was detected, the virtual processor was blocked. In the blocking method, latency of virtual halt exit of the virtual processor was so long that a problem of performance was caused. A virtual machine monitor selects either of a busy wait method for making repeatedly examination until the virtual halt state exits while the virtual processor stays on the physical processor and a blocking method for stopping execution of the virtual processor and scheduling other virtual processors on the physical processor while yielding the operating physical processor and checking off scheduling of the virtual processor to the physical processor, based on a virtual processor halt duration predicted value of the virtual processor which is an average value of latest N virtual processor halt durations of the virtual processor.
摘要翻译：在根据背景技术的计算机系统中，当检测到停止虚拟处理器的请求时，虚拟处理器被阻止。在阻塞方法中，虚拟处理器的虚拟停止退出的延迟太长，导致性能问题。虚拟机监视器选择忙等待方法进行重复检查，直到虚拟停止状态退出，而虚拟处理器停留在物理处理器上，并且阻止方法停止虚拟处理器的执行并且调度物理处理器上的其他虚拟处理器同时基于虚拟处理器停止作为虚拟处理器的最新N个虚拟处理器暂停持续时间的平均值的虚拟处理器的持续时间预测值，产生操作物理处理器并检查虚拟处理器到物理处理器的调度。

6. 发明授权

US08695007B2 Computer system and method of scheduling a virtual processor to run on physical processors based on the number of possessing cycles of each virtual computer 失效
标题翻译：基于每个虚拟计算机的拥有周期数目的计算机系统和调度虚拟处理器以在物理处理器上运行的方法
公开(公告)号：US08695007B2
公开(公告)日：2014-04-08
申请号：US13041012
申请日：2011-03-04
申请人： Shintaro Wada , Shuhei Matsumoto , Hironori Inoue , Kenichiro Yamato
发明人： Shintaro Wada , Shuhei Matsumoto , Hironori Inoue , Kenichiro Yamato
IPC分类号： G06F9/46 , G06F9/455 , G06F1/00
CPC分类号： G06F9/4881 , G06F9/45533 , G06F9/4893 , G06F2209/483 , Y02D10/24
摘要： A hypervisor calculates the total number of processor cycles (the number of processor cycles of one or more physical processors) in a first length of time based on the sum of the operating frequencies of the respective physical processors and the first length of time for each first length of time (for example, a scheduling initialization cycle T1, which will be explained further below). The hypervisor calculates for each virtual computer the number of possessing cycles, which is a value obtained by the total number of processor cycles being distributed in proportion to the service ratios of multiple virtual computers. In virtual processor scheduling, the hypervisor runs a virtual processor inside a virtual computer on any physical processor based on the number of hold cycles of each virtual computer.
摘要翻译：管理程序基于各个物理处理器的工作频率之和计算第一时间长度的处理器周期的总数（一个或多个物理处理器的处理器周期数）和每个第一时间的第一个时间长度时间长度（例如，调度初始化周期T1，将在下面进一步说明）。虚拟机管理程序为每个虚拟计算机计算拥有周期数，这是通过与多个虚拟计算机的服务比例成比例地分配的处理器周期总数而获得的值。在虚拟处理器调度中，虚拟机管理程序基于每个虚拟计算机的保持周期数，在任何物理处理器的虚拟计算机内运行虚拟处理器。

7. 发明授权

US08898675B2 Method of calculating processor utilization rate in SMT processor 有权
标题翻译：计算SMT处理器利用率的方法
公开(公告)号：US08898675B2
公开(公告)日：2014-11-25
申请号：US13312468
申请日：2011-12-06
申请人： Shuhei Matsumoto , Hironori Inoue , Shintaro Wada
发明人： Shuhei Matsumoto , Hironori Inoue , Shintaro Wada
IPC分类号： G06F9/46 , G06F11/34
CPC分类号： G06F11/3423 , G06F11/3433 , G06F2201/88
摘要： The method of calculating the processor utilization for each of logical processors in a computer, including the steps of: dividing the computation interval in which the processor utilization by each logical processor is to be calculated into a single task mode (ST) execution interval and a multitask mode (MT) execution interval, appropriately calculating them based on the before-and-after relation between two times; and adding the MT execution interval multiplied by a predetermined MT mode processor resource assignment ratio to the ST mode execution interval to obtain the processor utilization for the calculation-targeted logical processor in the computation interval.
摘要翻译：计算计算机中每个逻辑处理器的处理器利用率的方法，包括以下步骤：将每个逻辑处理器的处理器利用率的计算间隔划分为单个任务模式（ST）执行间隔和多任务模式（MT）执行间隔，根据两次之前和之后的关系适当地计算它们; 以及将MT执行间隔乘以预定的MT模式处理器资源分配比率到ST模式执行间隔，以在计算间隔中获得计算目标逻辑处理器的处理器利用率。

8. 发明申请

US20120174114A1 METHOD OF CALCULATING PROCESSOR UTILIZATION RATE IN SMT PROCESSOR 有权
标题翻译：计算SMT加工器中处理器利用率的方法
公开(公告)号：US20120174114A1
公开(公告)日：2012-07-05
申请号：US13312468
申请日：2011-12-06
申请人： SHUHEI MATSUMOTO , Hironori Inoue , Shintaro Wada
发明人： SHUHEI MATSUMOTO , Hironori Inoue , Shintaro Wada
IPC分类号： G06F9/50
CPC分类号： G06F11/3423 , G06F11/3433 , G06F2201/88
摘要： The method of calculating the processor utilization for each of logical processors in a computer, including the steps of: dividing the computation interval in which the processor utilization by each logical processor is to be calculated into a single task mode (ST) execution interval and a multitask mode (MT) execution interval, appropriately calculating them based on the before-and-after relation between two times; and adding the MT execution interval multiplied by a predetermined MT mode processor resource assignment ratio to the ST mode execution interval to obtain the processor utilization for the calculation-targeted logical processor in the computation interval.
摘要翻译：计算计算机中每个逻辑处理器的处理器利用率的方法，包括以下步骤：将每个逻辑处理器的处理器利用率的计算间隔划分为单个任务模式（ST）执行间隔和多任务模式（MT）执行间隔，根据两次之前和之后的关系适当地计算它们; 以及将MT执行间隔乘以预定的MT模式处理器资源分配比率到ST模式执行间隔，以在计算间隔中获得计算目标逻辑处理器的处理器利用率。

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