专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090267924A1 Drive Circuit, Display Device Provided With Such Drive Circuit and Method for Driving Display Device 有权
标题翻译：驱动电路，具有这种驱动电路的显示装置和驱动显示装置的方法
公开(公告)号：US20090267924A1
公开(公告)日：2009-10-29
申请号：US12085925
申请日：2006-09-07
申请人： Shinsaku Shimizu , Yuhichiroh Murakami
发明人： Shinsaku Shimizu , Yuhichiroh Murakami
IPC分类号： G09G5/00 , G11C19/00
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021 , G11C19/00 , G11C19/28
摘要： While an output signal of a flip-flop is inactive in a shift register, NAND circuits of clock pulse extracting sections prevent the performing of conduction switching operation in accordance with periodic level change of clock signals between a logical derivation path for High output and a logical derivation path for Low output, by input of the output signal.
摘要翻译：虽然触发器的输出信号在移位寄存器中不起作用，但是时钟脉冲提取部分的NAND电路根据用于高输出的逻辑导出路径和逻辑的逻辑导出路径之间的时钟信号的周期性电平改变来阻止执行导通切换操作通过输出信号输入低输出的推导路径。

2. 发明申请

US20100141641A1 SHIFT REGISTER 有权
标题翻译：移位寄存器
公开(公告)号：US20100141641A1
公开(公告)日：2010-06-10
申请号：US12733117
申请日：2008-05-15
申请人： Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Shinsaku Shimizu
发明人： Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Shinsaku Shimizu
IPC分类号： G09G5/00 , G11C19/00
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.
摘要翻译：在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。通过使用两相时钟信号并且其高电平周期彼此不重叠，复位信号产生电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平进入高层。在复位信号为高电平的期间，晶体管T3，T4进行节点的放电，输出信号的下拉。因此，可以获得省电移位寄存器，其将正常状态下的输出信号固定在低电平，而不允许通流通过。

3. 发明授权

US08362998B2 Drive circuit, display device provided with such drive circuit and method for driving display device 有权
标题翻译：驱动电路，具有这种驱动电路的显示装置和驱动显示装置的方法
公开(公告)号：US08362998B2
公开(公告)日：2013-01-29
申请号：US12085925
申请日：2006-09-07
申请人： Shinsaku Shimizu , Yuhichiroh Murakami
发明人： Shinsaku Shimizu , Yuhichiroh Murakami
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021 , G11C19/00 , G11C19/28
摘要： While an output signal of a flip-flop is inactive in a shift register, NAND circuits of clock pulse extracting sections prevent the performing of conduction switching operation in accordance with periodic level change of clock signals between a logical derivation path for High output and a logical derivation path for Low output, by input of the output signal.
摘要翻译：虽然触发器的输出信号在移位寄存器中不起作用，但是时钟脉冲提取部分的NAND电路根据用于高输出的逻辑导出路径和逻辑的逻辑导出路径之间的时钟信号的周期性电平改变来阻止执行导通切换操作通过输出信号输入低输出的推导路径。

4. 发明授权

US08269713B2 Shift register 有权
标题翻译：移位寄存器
公开(公告)号：US08269713B2
公开(公告)日：2012-09-18
申请号：US12733117
申请日：2008-05-15
申请人： Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Shinsaku Shimizu
发明人： Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Shinsaku Shimizu
IPC分类号： G09G3/36
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.
摘要翻译：在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。通过使用两相时钟信号并且其高电平周期彼此不重叠，复位信号产生电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平进入高层。在复位信号为高电平的期间，晶体管T3，T4进行节点的放电，输出信号的下拉。因此，可以获得省电移位寄存器，其将正常状态下的输出信号固定在低电平，而不允许通流通过。

5. 发明授权

US08493312B2 Shift register 有权
标题翻译：移位寄存器
公开(公告)号：US08493312B2
公开(公告)日：2013-07-23
申请号：US13571608
申请日：2012-08-10
申请人： Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Shinsaku Shimizu
发明人： Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Shinsaku Shimizu
IPC分类号： G09G3/36
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.
摘要翻译：在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。通过使用两相时钟信号并且其高电平周期彼此不重叠，复位信号产生电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平进入高层。在复位信号为高电平的期间，晶体管T3，T4进行节点的放电，输出信号的下拉。因此，可以获得省电移位寄存器，其将正常状态下的输出信号固定在低电平，而不允许通流通过。

6. 发明授权

US08427206B2 Buffer and display device 有权
标题翻译：缓冲和显示设备
公开(公告)号：US08427206B2
公开(公告)日：2013-04-23
申请号：US12734691
申请日：2008-08-19
申请人： Etsuo Yamamoto , Yuhichiroh Murakami , Yasushi Sasaki , Seijirou Gyouten , Shinsaku Shimizu
发明人： Etsuo Yamamoto , Yuhichiroh Murakami , Yasushi Sasaki , Seijirou Gyouten , Shinsaku Shimizu
IPC分类号： H03K3/00
CPC分类号： G09G3/3677 , G09G2310/0291 , G09G2330/021 , H03K19/0013 , H03K19/01714 , H03K19/018507 , H03K19/09441
摘要： A single-phase input including transistors all of which have only a single type of channel polarity, which buffer includes: a buffer section 32, including a first series circuit formed by two n-channel transistors connected to each other in series, a second series circuit formed by two n-channel transistors connected to each other in series at a connection point OUT, and a capacitor; and an inverted-signal generating section for generating an inverted-signal from an input signal, the inverted-signal generating section including n-channel transistors but no p-channel transistor, the input signal being inputted to respective gates of the transistors, the inverted-signal being inputted to a gate of the transistor 4, and an output signal being outputted via the connection point OUT. With the buffer, it is possible that a consumption current be reduced and a current drive for a load is enhanced.
摘要翻译：包括晶体管的单相输入，所述晶体管仅具有单一类型的沟道极性，该缓冲器包括：缓冲器部分32，包括由串联连接的两个n沟道晶体管构成的第一串联电路，第二系列由在连接点OUT处彼此串联连接的两个n沟道晶体管形成的电路，以及电容器; 以及反相信号生成部，用于从输入信号产生反相信号，所述反相信号生成部包括n沟道晶体管，但不包括p沟道晶体管，所述输入信号被输入到所述晶体管的各个栅极，所述反相信号生成部信号被输入到晶体管4的栅极，并且输出信号经由连接点OUT输出。使用缓冲器，可以减少消耗电流并且增加用于负载的电流驱动。

7. 发明申请

US20100141642A1 SHIFT REGISTER 有权
标题翻译：移位寄存器
公开(公告)号：US20100141642A1
公开(公告)日：2010-06-10
申请号：US12733119
申请日：2008-05-15
申请人： Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Shinsaku Shimizu
发明人： Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Shinsaku Shimizu
IPC分类号： G09G5/00 , G11C19/00
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a shift register which performs discharge of a node and pull-down of an output signal and achieves a small area and low power consumption without using an output signal from a subsequent circuit.
摘要翻译：在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。通过使用高电平周期彼此不重叠的两相时钟信号，复位信号生成电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平高层次。在复位信号处于高电平的期间，晶体管执行节点的放电和输出信号的下拉。因此，可以获得执行节点放电和输出信号下拉的移位寄存器，并且在不使用来自后续电路的输出信号的情况下实现小面积和低功耗。

8. 发明申请

US20120307959A1 SHIFT REGISTER 有权
标题翻译：移位寄存器
公开(公告)号：US20120307959A1
公开(公告)日：2012-12-06
申请号：US13571608
申请日：2012-08-10
申请人： Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Shinsaku Shimizu
发明人： Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Shinsaku Shimizu
IPC分类号： G11C19/00
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.
摘要翻译：在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。通过使用两相时钟信号并且其高电平周期彼此不重叠，复位信号产生电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平进入高层。在复位信号为高电平的期间，晶体管T3，T4进行节点的放电，输出信号的下拉。因此，可以获得省电移位寄存器，其将正常状态下的输出信号固定在低电平，而不允许通流通过。

9. 发明授权

US08269714B2 Shift register 有权
标题翻译：移位寄存器
公开(公告)号：US08269714B2
公开(公告)日：2012-09-18
申请号：US12733119
申请日：2008-05-15
申请人： Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Shinsaku Shimizu
发明人： Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Shinsaku Shimizu
IPC分类号： G09G3/36
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a shift register which performs discharge of a node and pull-down of an output signal and achieves a small area and low power consumption without using an output signal from a subsequent circuit.
摘要翻译：在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。通过使用高电平周期彼此不重叠的两相时钟信号，复位信号生成电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平高层次。在复位信号处于高电平的期间，晶体管执行节点的放电和输出信号的下拉。因此，可以获得执行节点放电和输出信号下拉的移位寄存器，并且在不使用来自后续电路的输出信号的情况下实现小面积和低功耗。

10. 发明授权

US09149409B2 Back kneading device and chair-type massage apparatus equipped with the back kneading device 有权
标题翻译：背部捏合装置和配有背部捏合装置的椅子式按摩器具
公开(公告)号：US09149409B2
公开(公告)日：2015-10-06
申请号：US13551256
申请日：2012-07-17
申请人： Koichi Numata , Shinsaku Shimizu , Fumitaka Ishiguro
发明人： Koichi Numata , Shinsaku Shimizu , Fumitaka Ishiguro
IPC分类号： A61H15/00 , A61H7/00 , A61H23/00
CPC分类号： A61H7/007 , A61H15/0078 , A61H23/006 , A61H2015/0014 , A61H2201/0149 , A61H2201/1623 , A61H2201/1664 , A61H2201/1669 , A61H2201/1676 , A61H2201/5035 , A61H2205/081
摘要： The back kneading device mounted in the chair-type massage apparatus comprises: the massage mechanism including paired right-hand and left-hand massage members having the treatment element for massage and the driving section for transmitting massage action to the massage member; the base member for supporting the massage mechanism, with the massage member pointing forward; the vertical movement mechanism for moving the base member in the vertical direction in the backrest; and the protruding-amount varying mechanism for moving the massage member so that protrusion amount of the treatment element in the front-rear direction can be varied.
摘要翻译：安装在椅子式按摩器中的背部捏合装置具备：按摩机构，具有具有按摩用处理元件的成对的右手和左侧的按摩器，以及用于向按摩部件发送按摩动作的驱动部; 用于支撑按摩机构的基座部件，按摩部件指向前方; 用于在靠背中沿垂直方向移动基底构件的垂直移动机构; 以及用于移动按摩部件的突出量可变机构，使得处理元件在前后方向上的突出量可以改变。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式