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1. 发明授权

US4199470A Material for recovering uranium and method for recovering a uranium solution of high purity and high concentration, using the same 失效
标题翻译：用于回收铀的材料和回收高纯度和高浓度的铀溶液的方法
公开(公告)号：US4199470A
公开(公告)日：1980-04-22
申请号：US903144
申请日：1978-05-05
申请人： Shinichi Yasuda , Takayasu Niwa , Takayuki Kurohara
发明人： Shinichi Yasuda , Takayasu Niwa , Takayuki Kurohara
IPC分类号： B01J41/04 , C22B60/02 , B01D59/30
CPC分类号： B01J41/046 , C22B60/0265
摘要： Uranium is recovered from its solution through contact with a uranium-recovering material of higher resistance to water and higher mechanical strength comprising a weakly basic anion exchange resin having pyridine nuclei at its main chain or side chain, and a crossed-linked polymer structure with a high uranium selectivity at a high uranium-adsorbing speed.
摘要翻译：通过与其具有较高抗水性和较高机械强度的铀回收材料的接触从其溶液中回收铀，其包含在其主链或侧链上具有吡啶核的弱碱性阴离子交换树脂和具有吡啶核的交联聚合物结构在高铀吸附速度下的高铀选择性。

2. 发明授权

US08601012B2 Automatic search and transfer apparatus and automatic search and transfer system 有权
标题翻译：自动搜索和传输设备和自动搜索和传输系统
公开(公告)号：US08601012B2
公开(公告)日：2013-12-03
申请号：US12737933
申请日：2008-09-11
申请人： Shinichi Yasuda , Koichi Abe , Shogo Tsubouchi
发明人： Shinichi Yasuda , Koichi Abe , Shogo Tsubouchi
IPC分类号： G06F17/30
CPC分类号： G06F17/30029 , G06F17/30038
摘要： An automatic search and transfer apparatus that automatically searches for and transfers data one or more computers connected via a network, that includes a keyword input section that inputs at least one keyword, a search section that searches for data including the at least one keyword and acquires attribute data of concerned data from the one or more computers connected via the network, a reporting section that reports information relating to the concerned data to a user, a reception section that receives the concerned data from one or more computers, and a data storage section that stores the data. The reporting section reports acquisition of the attribute data to the user when the attribute data is acquired, and the reception section starts reception of the concerned data after the reporting section has reported the acquisition of the attribute data of the concerned data to the user.
摘要翻译：一种自动搜索和传送装置，其自动搜索和传送经由网络连接的一个或多个计算机的数据，其包括输入至少一个关键字的关键字输入部分，搜索包括至少一个关键字的数据的搜索部分，并获取来自经由网络连接的一台以上的计算机的有关数据的属性数据，向用户报告与有关数据有关的信息的报告部，从一台以上的计算机接收有关数据的接收部，以及数据存储部存储数据。报告部分在获取属性数据时向用户报告属性数据的获取，并且在报告部分已经向用户报告了有关数据的属性数据的获取之后，接收部分开始接收相关数据。

3. 发明授权

US08307022B2 Random number generating device 有权
标题翻译：随机数生成装置
公开(公告)号：US08307022B2
公开(公告)日：2012-11-06
申请号：US12130567
申请日：2008-05-30
申请人： Mari Matsumoto , Ryuji Ohba , Shinichi Yasuda , Shinobu Fujita
发明人： Mari Matsumoto , Ryuji Ohba , Shinichi Yasuda , Shinobu Fujita
IPC分类号： G06F1/02
CPC分类号： G06F7/588 , H03K3/84
摘要： A random number generating device includes: a pulse voltage generator configured to generate a pulse voltage having an amplitude of 26 mV or more; a random noise generating element including source and drain regions formed at a distance from each other on a semiconductor substrate, a tunnel insulating film formed on a portion of the semiconductor substrate located between the source region and the drain region, and a gate electrode formed above the tunnel insulating film and to which the pulse voltage is applied, the random noise generating element configured to generate a random noise contained in a current flowing between the source region and the drain region; and a random number generating unit configured to generate a random number signal based on the random noise.
摘要翻译：随机数生成装置包括：脉冲电压发生器，被配置为产生具有26mV或更大幅度的脉冲电压; 包括形成在半导体衬底上彼此间隔一定距离的源极和漏极区域的随机噪声产生元件，形成在位于源极区域和漏极区域之间的半导体衬底的一部分上的隧道绝缘膜以及形成在栅极电极上的栅电极隧道绝缘膜，并且施加脉冲电压，所述随机噪声产生元件被配置为产生包含在源极区域和漏极区域之间的电流中的随机噪声; 以及随机数生成单元，被配置为基于随机噪声生成随机数信号。

4. 发明申请

US20110205780A1 Semiconductor Integrated Circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20110205780A1
公开(公告)日：2011-08-25
申请号：US12880758
申请日：2010-09-13
申请人： Shinichi Yasuda , Keiko Abe , Shinobu Fujita
发明人： Shinichi Yasuda , Keiko Abe , Shinobu Fujita
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2013/0073 , G11C2213/75 , H03K19/17728 , H03K19/1776
摘要： In one embodiment, a semiconductor integrated circuit includes a first resistive-change element, a second resistive-change element and a first switching element. The first resistive-change element includes one end having a first polarity connected to a first power source. The first resistive-change element includes another end having a second polarity connected to an output node. The second resistive-change element includes one end having the second polarity connected to the output node. The first switching element includes a first terminal connected to another end of the second resistive-change element. The first switching element includes a second terminal connected to a second power source.
摘要翻译：在一个实施例中，半导体集成电路包括第一电阻变化元件，第二电阻变化元件和第一开关元件。第一电阻变化元件包括具有连接到第一电源的第一极性的一端。第一电阻变化元件包括具有连接到输出节点的第二极性的另一端。第二电阻变化元件包括具有连接到输出节点的第二极性的一端。第一开关元件包括连接到第二电阻变化元件的另一端的第一端子。第一开关元件包括连接到第二电源的第二端子。

5. 发明授权

US07795920B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07795920B2
公开(公告)日：2010-09-14
申请号：US12367379
申请日：2009-02-06
申请人： Shinichi Yasuda
发明人： Shinichi Yasuda
IPC分类号： H03K19/00
CPC分类号： G01R31/31725 , G01R31/31727
摘要： A semiconductor integrated circuit includes a flipflop holding and outputting input data according to a clock, the flipflop having: an input end to which data is input; an output end from which data is output; a first logic gate connected between the input end and the output end, the first logic gate operating according to the clock; a second logic gate connected between the first logic gate and the output end, the second logic gate operating according to the clock; and a buffer circuit. An input of the buffer circuit is connected to a node between the first logic gate and the input end. An output of the buffer circuit is connected to a node in an output side of the first logic gate. The buffer circuit transitions according to an enable signal from a high impedance state to a state in which a signal can be transmitted.
摘要翻译：一种半导体集成电路包括触发器，其保持并根据时钟输出输入数据，所述触发器具有：输入数据的输入端; 输出数据的输出端; 连接在输入端和输出端之间的第一逻辑门，第一逻辑门根据时钟工作; 连接在第一逻辑门和输出端之间的第二逻辑门，第二逻辑门根据时钟工作; 和缓冲电路。缓冲电路的输入连接到第一逻辑门和输入端之间的节点。缓冲电路的输出连接到第一逻辑门的输出侧的节点。缓冲电路根据从高阻抗状态的使能信号转换到可以发送信号的状态。

6. 发明授权

US07392271B2 Random number generating circuit, semiconductor integrated circuit, IC card and information terminal device 有权
标题翻译：随机数发生电路，半导体集成电路，IC卡和信息终端装置
公开(公告)号：US07392271B2
公开(公告)日：2008-06-24
申请号：US10919291
申请日：2004-08-17
申请人： Shinichi Yasuda , Shinobu Fujita
发明人： Shinichi Yasuda , Shinobu Fujita
IPC分类号： G06F1/02
CPC分类号： G06F7/58
摘要： A random number generating circuit receives as input a first digital random number signal generated at a first generating rate and produces as output a second digital random number signal having a second generating rate that is twice as high as the first generating rate. A semiconductor integrated circuit, an IC card and an information terminal device comprising the random number circuit is provided.
摘要翻译：随机数产生电路接收以第一产生速率产生的第一数字随机数信号作为输出，产生第二数字随机数信号，该第二数字随机数信号的第二发生速率是第一发生速率的两倍。提供了包括随机数电路的半导体集成电路，IC卡和信息终端装置。

7. 发明授权

US07184297B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07184297B2
公开(公告)日：2007-02-27
申请号：US11165404
申请日：2005-06-24
申请人： Shinichi Yasuda , Keiko Abe
发明人： Shinichi Yasuda , Keiko Abe
IPC分类号： G11C11/00 , G11C27/00 , G11C5/06 , G11C11/34
CPC分类号： G11C11/14
摘要： A semiconductor memory includes: a first node and a second node; a first MIS transistor, having first conductive carrier flows, including a source electrode connected to a first power supply, a drain electrode connected to the second node, and a gate electrode connected to the first node; a second MIS transistor, having second conductive carrier flows, including a source electrode connected to a second power supply, a drain electrode connected to the second node, and a gate electrode connected to the first node; and a resistance change element connected between the first node and the second node and having a variable resistance due to the direction in which a voltage is applied, wherein information is written in the resistance change element by applying a voltage between the first and the second node, and stored information is read out by applying a low or high input voltage to the first node and reading out a voltage difference in the second node.
摘要翻译：半导体存储器包括：第一节点和第二节点; 具有第一导电载流子的第一MIS晶体管，包括连接到第一电源的源电极，连接到第二节点的漏电极和连接到第一节点的栅电极; 具有第二导电载流子的第二MIS晶体管，包括连接到第二电源的源电极，连接到第二节点的漏电极和连接到第一节点的栅电极; 以及连接在第一节点和第二节点之间并且由于施加电压的方向而具有可变电阻的电阻变化元件，其中通过在第一和第二节点之间施加电压将信息写入电阻变化元件并且通过向第一节点施加低或高输入电压并读出第二节点中的电压差来读出存储的信息。

8. 发明授权

US5223304A Process for fabricating magnetic disks 失效
标题翻译：磁盘制造工艺
公开(公告)号：US5223304A
公开(公告)日：1993-06-29
申请号：US987817
申请日：1992-12-09
申请人： Shinichi Yasuda , Atsushi Tamura , Tadahito Kanaizuka
发明人： Shinichi Yasuda , Atsushi Tamura , Tadahito Kanaizuka
IPC分类号： B24B21/00 , C23C14/02 , G11B5/73 , G11B5/84
CPC分类号： G11B5/7315 , C23C14/028 , G11B5/8404 , Y10S428/90 , Y10S428/928
摘要： A process for fabricating a magnetic disk which comprises texturing a magnetic disk substrate made of a non-magnetic material having provided on the surface thereof a hard layer of a metal or an oxide to thereby provide fine irregularities on the surface of said substrate, followed by establishing thereon a magnetic recording layer comprising a film of a ferromagnetic metal, wherein said texturing is carried out using a processing solution comprising an aqueous solution of a surface active agent having dispersed therein diamond abrasive grains substantially only not larger than 4 .mu.m in grain diameter.
摘要翻译：一种制造磁盘的方法，该方法包括对由非磁性材料制成的磁盘衬底进行纹理化，该非磁性材料在其表面上设置有金属或氧化物的硬层，从而在所述衬底的表面上提供细小的不规则性，在其上建立包括铁磁性金属膜的磁记录层，其中所述纹理使用包含基本上不大于4μm的颗粒直径的金刚石磨粒的表面活性剂的水溶液的处理溶液进行。

9. 发明授权

US08970249B2 Look-up table circuit 有权
标题翻译：查询表电路
公开(公告)号：US08970249B2
公开(公告)日：2015-03-03
申请号：US13606041
申请日：2012-09-07
申请人： Masato Oda , Shinichi Yasuda
发明人： Masato Oda , Shinichi Yasuda
IPC分类号： H03K19/173
CPC分类号： G11C5/148
摘要： One embodiment provides a look-up table circuit, including: 2i memories, a half of which constituting a first memory group, the other half of which constituting a second memory group; first to i-th input terminals to which first to i-th input signals are input, respectively; a first output terminal; a switch group that selectively connects one of the memories to the first output terminal according to the first to i-th input signals; a first power-off switch that shuts off power supply to the first memory group in response to one of the first to i-th input signals; and a second power-off switch that shuts off power supply to the second memory group in response to the one of the first to i-th input signals.
摘要翻译：一个实施例提供了一种查找表电路，包括：2i个存储器，其中一半构成第一存储器组，另一半构成第二存储器组; 分别输入第一至第i输入信号的第一至第i输入端子; 第一输出端子; 开关组，根据第一至第i输入信号有选择地将一个存储器连接到第一输出端; 第一断电开关，其响应于第一至第i输入信号中的一个切断对第一存储器组的电源; 以及第二断电开关，其响应于所述第一至第i输入信号之一而切断对所述第二存储器组的电源。

10. 发明授权

US08680887B2 Nonvolatile configuration memory 失效
标题翻译：非易失配置存储器
公开(公告)号：US08680887B2
公开(公告)日：2014-03-25
申请号：US13419205
申请日：2012-03-13
申请人： Keiko Abe , Shinichi Yasuda , Kumiko Nomura , Shinobu Fujita
发明人： Keiko Abe , Shinichi Yasuda , Kumiko Nomura , Shinobu Fujita
IPC分类号： H03K19/177 , G11C11/34 , G11C16/04 , G11C11/00
CPC分类号： H03K19/1776 , G11C11/412 , G11C14/0063
摘要： According to one embodiment, a memory includes a first P-channel FET having a gate connected to a second output node, a source applied to a first potential, and a drain connected to the first output node, a second P-channel FET having a gate connected to a first output node, a source applied to the first potential, and a drain connected to the second output node, a first N-channel FET having a control gate connected to a first word line, a source applied to a second potential lower than the first potential, a drain connected to the first output node, and a threshold changed by data in a storage layer, and a second N-channel FET having a control gate connected to a second word line, a source applied to the second potential, a drain connected to the second output node, and a threshold changed by data in a storage layer.
摘要翻译：根据一个实施例，存储器包括：第一P沟道FET，其具有连接到第二输出节点的栅极，施加到第一电位的源极和连接到第一输出节点的漏极;第二P沟道FET，其具有连接到第一输出节点的源极，施加到第一电位的源极和连接到第二输出节点的漏极，具有连接到第一字线的控制栅极的第一N沟道FET，施加到第二电位的源极低于第一电位的漏极，连接到第一输出节点的漏极和由存储层中的数据改变的阈值，以及具有连接到第二字线的控制栅极的第二N沟道FET，施加到第二电压的源极电位，连接到第二输出节点的漏极以及由存储层中的数据改变的阈值。

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