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1. 发明授权

US07529595B2 Method of controlling substrate processing apparatus and substrate processing apparatus 有权
标题翻译：控制基板处理装置和基板处理装置的方法
公开(公告)号：US07529595B2
公开(公告)日：2009-05-05
申请号：US10581073
申请日：2004-11-30
申请人： Shinichi Shinozuka , Shigeki Wada , Masami Yamashita
发明人： Shinichi Shinozuka , Shigeki Wada , Masami Yamashita
IPC分类号： G06F19/00
CPC分类号： H01L21/67745 , G03F7/162 , G03F7/3021 , H01L21/67276
摘要： It is an object of the present invention to realize, in a coating and developing apparatus including an inspection section, reduction in the startup time, cost reduction, and an improved operating rate of the inspection section.In the present invention, a control program of the coating and developing apparatus is set such that a processing flow and an inspection flow can be independently executed, the processing flow being a flow in which a substrate is carried to a processing station from a cassette station to be processed in the processing station and an aligner and thereafter is returned to the cassette station, and the inspection flow being a flow in which the substrate is carried from the cassette station to an inspection station to be inspected there, and is thereafter returned to the cassette station. At startup of the coating and developing apparatus, the inspection flow and the processing flow are executed, and an evaluation work of an inspection unit of the inspection station and an adjustment work of a processing unit in the processing station can proceed simultaneously. When the inspection station is idle, a substrate can be carried from an external part to the cassette station to be inspected there.
摘要翻译：本发明的目的是在包括检查部分的涂覆和显影装置中实现起动时间的减少，成本降低和检查部分的提高的操作速度。在本发明中，涂布显影装置的控制程序被设定为能够独立地执行处理流程和检查流程，处理流程是将基板从盒式磁带机搬送到加工站的流程在处理站和对准器中处理，然后返回到盒式站，并且检查流程是将基板从盒式站被运送到在那里进行检查的检查站的流程，然后返回到盒式电台。在涂装和显影装置启动时，执行检查流程和处理流程，并且检查站的检查单元和处理站中的处理单元的调整工作的评估工作可以同时进行。当检查站空闲时，可以将基板从外部部件运送到要在那里进行检查的卡带站。

2. 发明申请

US20070088450A1 Method of controlling substrate processing apparatus and substrate processing apparatus 有权
标题翻译：控制基板处理装置和基板处理装置的方法
公开(公告)号：US20070088450A1
公开(公告)日：2007-04-19
申请号：US10581073
申请日：2004-11-30
申请人： Shinichi Shinozuka , Shigeki Wada , Masami Yamashita
发明人： Shinichi Shinozuka , Shigeki Wada , Masami Yamashita
IPC分类号： G06F19/00
CPC分类号： H01L21/67745 , G03F7/162 , G03F7/3021 , H01L21/67276
摘要： It is an object of the present invention to realize, in a coating and developing apparatus including an inspection section, reduction in the startup time, cost reduction, and an improved operating rate of the inspection section. In the present invention, a control program of the coating and developing apparatus is set such that a processing flow and an inspection flow can be independently executed, the processing flow being a flow in which a substrate is carried to a processing station from a cassette station to be processed in the processing station and an aligner and thereafter is returned to the cassette station, and the inspection flow being a flow in which the substrate is carried from the cassette station to an inspection station to be inspected there, and is thereafter returned to the cassette station. At startup of the coating and developing apparatus, the inspection flow and the processing flow are executed, and an evaluation work of an inspection unit of the inspection station and an adjustment work of a processing unit in the processing station can proceed simultaneously. When the inspection station is idle, a substrate can be carried from an external part to the cassette station to be inspected there.
摘要翻译：本发明的目的是在包括检查部分的涂覆和显影装置中实现起动时间的减少，成本降低和检查部分的提高的操作速度。在本发明中，涂布显影装置的控制程序被设定为能够独立地执行处理流程和检查流程，处理流程是将基板从盒式磁带机搬送到加工站的流程在处理站和对准器中处理，然后返回到盒式站，并且检查流程是将基板从盒式站被运送到在那里进行检查的检查站的流程，然后返回到盒式电台。在涂装和显影装置启动时，执行检查流程和处理流程，并且检查站的检查单元和处理站中的处理单元的调整工作的评估工作可以同时进行。当检查站空闲时，可以将基板从外部部件运送到要在那里进行检查的卡带站。

3. 发明授权

US08170093B2 Equalizing filter circuit 有权
标题翻译：均衡滤波电路
公开(公告)号：US08170093B2
公开(公告)日：2012-05-01
申请号：US12439139
申请日：2007-08-24
申请人： Shigeki Wada
发明人： Shigeki Wada
IPC分类号： H03H7/30
CPC分类号： H03H15/00 , H03H2015/007 , H04B3/142 , H04B3/145
摘要： An equalizing filter circuit includes a first transmission line in which a plurality of first delay devices 104a are connected in cascade to input terminal 101, a second transmission line in which a plurality of second delay devices 107a are connected in cascade to output terminal 102, a plurality of weighting circuits 105a connected in parallel between the first transmission line and the second transmission line and having a gain which is adjustable by setting coefficients, and variable adjusting circuit 108a arranged at the output side of at least one of weighting circuits 105a for correcting a fluctuation of the output characteristics of the weighting circuits.
摘要翻译：均衡滤波电路包括多个第一延迟装置104a级联连接到输入端101的第一传输线，多个第二延迟装置107a串联连接到输出端102的第二传输线，多个加权电路105a并联连接在第一传输线和第二传输线之间，并具有通过设定系数可调整的增益;以及可变调节电路108a，布置在至少一个加权电路105a的输出侧，用于校正加权电路的输出特性波动。

4. 发明申请

US20090262796A1 EQUALIZING FILTER CIRCUIT 有权
标题翻译：均衡滤波电路
公开(公告)号：US20090262796A1
公开(公告)日：2009-10-22
申请号：US12439139
申请日：2007-08-24
申请人： Shigeki Wada
发明人： Shigeki Wada
IPC分类号： H03H7/40 , H03K5/159 , H03H7/30 , H04B3/04
CPC分类号： H03H15/00 , H03H2015/007 , H04B3/142 , H04B3/145
摘要： An equalizing filter circuit includes a first transmission line in which a plurality of first delay devices 104a are connected in cascade to input terminal 101, a second transmission line in which a plurality of second delay devices 107a are connected in cascade to output terminal 102, a plurality of weighting circuits 105a connected in parallel between the first transmission line and the second transmission line and having a gain which is adjustable by setting coefficients, and variable adjusting circuit 108a arranged at the output side of at least one of weighting circuits 105a for correcting a fluctuation of the output characteristics of the weighting circuits.
摘要翻译：均衡滤波电路包括多个第一延迟装置104a级联连接到输入端101的第一传输线，多个第二延迟装置107a串联连接到输出端102的第二传输线，多个加权电路105a并联连接在第一传输线和第二传输线之间，并具有通过设定系数可调整的增益;以及可变调节电路108a，布置在至少一个加权电路105a的输出侧，用于校正加权电路的输出特性波动。

5. 发明申请

US20050231258A1 Static flip-flop circuit 审中-公开
标题翻译：静态触发电路
公开(公告)号：US20050231258A1
公开(公告)日：2005-10-20
申请号：US10519457
申请日：2003-06-24
申请人： Yasuyuki Suzuki , Shigeki Wada , Yasushi Amamiya
发明人： Yasuyuki Suzuki , Shigeki Wada , Yasushi Amamiya
IPC分类号： H03K3/3562 , H03K3/012 , H03K3/289 , H03K3/037
CPC分类号： H03K3/289 , H03K3/012
摘要： Master circuit 1 and slave circuit 2 are designed so that the transistors constituting data-hold differential pairs are smaller in size than the transistors constituting data reading differential pairs. Further, the flip-flop circuit is adapted to operate in an operating speed range in which the currents through the data-hold differential pairs are lower than the currents through the data reading differential pairs, and the currents through the data-hold differential pairs are equal to or lower than the permissible current level of the transistors that constitute the data-hold differential pairs.
摘要翻译：主电路1和从电路2被设计成构成数据保持差分对的晶体管的尺寸小于构成数据读差分对的晶体管。此外，触发器电路适于在通过数据保持差分对的电流低于通过数据读取差分对的电流的工作速度范围内工作，并且通过数据保持差分对的电流为等于或低于构成数据保持差分对的晶体管的允许电流电平。

6. 发明授权

US06214744B1 Method for manufacturing semiconductor device capable of improving etching rate ratio of insulator to refractory metal 失效
$Method for manufacturing semiconductor device capable of improving etching rate ratio of insulator to refractory metal$
标题翻译：能够提高绝缘体与难熔金属的蚀刻速度比的半导体装置的制造方法
公开(公告)号：US06214744B1
公开(公告)日：2001-04-10
申请号：US09407655
申请日：1999-09-28
申请人： Shigeki Wada
发明人： Shigeki Wada
IPC分类号： H01L21302
CPC分类号： H01L21/31116
摘要： In a method for manufacturing a semiconductor device, an insulating layer is formed on a refractory metal layer, and a contact hole in the insulating layer by a dry etching process using an etching gas. The etching gas includes one of: a mixture gas of fluorocarbon and hydrogen; a mixture gas of hydrofluorocarbon and hydrogen; a gas of hydrofluorocarbon; and a fluorocarbon gas except for CF4.
摘要翻译：在制造半导体器件的方法中，通过使用蚀刻气体的干法蚀刻工艺，在耐火金属层和绝缘层中形成绝缘层。蚀刻气体包括以下之一：碳氟化合物和氢气的混合气体;氢氟烃和氢气的混合气体;氢氟烃气体; 和CF4以外的碳氟化合物气体。

7. 发明授权

US08571095B2 Equalization filter and distortion compensating method 有权
标题翻译：均衡滤波器和失真补偿方法
公开(公告)号：US08571095B2
公开(公告)日：2013-10-29
申请号：US12520468
申请日：2007-11-30
申请人： Shigeki Wada
发明人： Shigeki Wada
IPC分类号： H03H7/30
CPC分类号： H04B3/142 , H04B10/25073
摘要： An equalization filter is provided for solving the problem in which there is a limited range in which compensated for distortion of a transmission signal can be made.Measuring instrument 104 measures a distortion quantity which characterizes distortion of the transmission signal. Comparator 105a generates a differential signal which indicates the difference between the transmission signal and a compensation signal. Delay device 105b delays the differential signal based on the distortion quantity measured by measurement instrument 104 and generates the compensation signal.
摘要翻译：提供了一种均衡滤波器，用于解决可以进行补偿发送信号失真的有限范围的问题。测量仪器104测量表征发送信号失真的失真量。比较器105a产生指示发送信号和补偿信号之间的差的差分信号。延迟装置105b基于由测量仪器104测量的失真量来延迟差分信号，并产生补偿信号。

8. 发明授权

US07167769B2 Inline connection setting method and device and substrate processing devices and substrate processing system 有权
标题翻译：在线连接设置方法及设备及基板处理装置及基板处理系统
公开(公告)号：US07167769B2
公开(公告)日：2007-01-23
申请号：US10546385
申请日：2004-03-01
申请人： Shigeki Wada
发明人： Shigeki Wada
IPC分类号： G06F19/00
CPC分类号： H01L21/67276 , G03F7/70508 , G03F7/70991
摘要： It at least includes a step at which a coating and developing apparatus requests an exposure apparatus, connected inline thereto, to transfer profile information which is information relating to the exposure apparatus, a step at which the coating and developing apparatus receives the profile information from the exposure apparatus, and a step at which the coating and developing apparatus selects a software file to be used in the coating and developing apparatus, in association with the profile information.
摘要翻译：它至少包括涂覆和显影装置请求连接在其上的曝光装置以传送与曝光装置有关的信息的简档信息的步骤，涂布和显影装置从其中接收简档信息的步骤曝光装置，以及涂布和显影装置与外形信息相关联地选择要在涂装和显影装置中使用的软件文件的步骤。

9. 发明申请

US20050253653A1 Feedback amplifier having amplified signal path and feedback signal path separated 有权
标题翻译：反馈放大器具有放大的信号路径和反馈信号路径分离
公开(公告)号：US20050253653A1
公开(公告)日：2005-11-17
申请号：US10516102
申请日：2003-05-30
申请人： Shigeki Wada , Yasuhiro Watanabe
发明人： Shigeki Wada , Yasuhiro Watanabe
IPC分类号： H03F1/48 , H03F3/08 , H03F3/50 , H03F3/45
CPC分类号： H03F3/082 , H03F3/505 , H03F2203/45612 , H03F2203/45652 , H03F2203/45722
摘要： A separation circuit part is used to separate an amplified signal path from a feedback signal path. An amplifier circuit part comprises a resistor-loaded common-source FET, a level adjustment diode and a source-follower circuit. The separation circuit part comprises a source-follower circuit, an output part of which is connected to a feedback circuit part comprising a resistor, thereby forming a feedback signal path to an input terminal of the amplifier circuit part. The signal separation circuit is used to separate the amplified signal path from the feedback signal path, thereby reducing the loads of the signal paths. In this way, the loads of the amplified signal and feedback signal paths are reduced. The delay time to be added in the separation circuit part is adjusted to cause the frequency range where the feedback changes from a negative feedback to a positive feedback to be coincident with the frequency range where the gain of the negative feedback amplifier part decreases, thereby realizing a wide band of gain.
摘要翻译：分离电路部分用于将放大的信号路径与反馈信号路径分离。放大器电路部分包括电阻负载共源FET，电平调节二极管和源极跟随器电路。分离电路部分包括源极跟随器电路，其输出部分连接到包括电阻器的反馈电路部分，从而形成到放大器电路部分的输入端的反馈信号路径。信号分离电路用于将放大的信号路径与反馈信号路径分开，从而减少信号路径的负载。以这种方式，减小放大信号和反馈信号路径的负载。调整在分离电路部分中添加的延迟时间，使得反馈从负反馈变化到正反馈的频率范围与负反馈放大器部分的增益减小的频率范围一致，从而实现一个广泛的收益。

10. 发明授权

US06087256A Method for manufacturing modified T-shaped gate electrode 失效
标题翻译：制造改性T型栅电极的方法
公开(公告)号：US06087256A
公开(公告)日：2000-07-11
申请号：US992766
申请日：1997-12-17
申请人： Shigeki Wada
发明人： Shigeki Wada
IPC分类号： H01L29/41 , H01L21/285 , H01L21/329 , H01L21/335 , H01L21/338 , H01L21/768 , H01L29/423 , H01L29/812 , H01L21/44
CPC分类号： H01L21/76831 , H01L21/2855 , H01L21/76813 , H01L21/76877 , H01L21/7688 , H01L21/76885 , H01L29/42316 , H01L29/66143 , H01L29/66462 , H01L29/66863
摘要： In a method for manufacturing a semiconductor device, an insulating layer is formed on a semiconductor substrate, and a refractory metal is formed layer on the insulating layer. Then, a first opening is perforated in the refractory metal layer, and a part of the insulating layer is etched by using the refractory metal as a mask. Then, a second opening is perforated in the refractory metal layer. The second opening is superposed onto the first opening and is larger than the first opening. Then, the insulating layer is again etched by using the refractory metal layer as a mask, so that a T-shaped opening is perforated in the insulating layer. Finally, a modified T-shaped gate metal electrode is formed on the insulating layer having the T-shaped opening.
摘要翻译：在半导体装置的制造方法中，在半导体基板上形成绝缘层，在绝缘层上形成难熔金属层。然后，在难熔金属层中穿过第一开口，并且通过使用难熔金属作为掩模来蚀刻绝缘层的一部分。然后，在难熔金属层中穿过第二开口。第二开口叠置在第一开口上并且大于第一开口。然后，通过使用难熔金属层作为掩模，再次对绝缘层进行蚀刻，从而在绝缘层中穿孔T形开口。最后，在具有T形开口的绝缘层上形成改进的T形栅极金属电极。

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