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1. 发明授权

US4905068A Semiconductor device having interconnection layers of T-shape cross section 失效
标题翻译：具有T形横截面的互连层的半导体器件
公开(公告)号：US4905068A
公开(公告)日：1990-02-27
申请号：US143400
申请日：1988-01-13
申请人： Shinichi Satoh , Makoto Hirayama , Masao Nagatomo , Ikuo Ogoh , Yoshikazu Ohno , Masato Fujinaga
发明人： Shinichi Satoh , Makoto Hirayama , Masao Nagatomo , Ikuo Ogoh , Yoshikazu Ohno , Masato Fujinaga
IPC分类号： H01L21/3205 , H01L21/8242 , H01L23/52 , H01L23/522 , H01L27/10 , H01L27/108
CPC分类号： H01L23/5222 , H01L2924/0002
摘要： A cell plate (6) is formed on a main surface of a semiconductor substrate (7) with an insulating film (8) interposed therebetween and an interconnection (1) having T-shape cross section is formed on the cell plate (6) with an interlayer insulating film (11) interposed therebetween. An upper insulating film (12) is formed to cover the interconnection (1).
摘要翻译：在半导体衬底（7）的主表面上形成有绝缘膜（8）的电池板（6），并且在电池板（6）上形成具有T形横截面的互连（1）夹在其间的层间绝缘膜（11）。形成上绝缘膜（12）以覆盖互连（1）。

2. 发明授权

US08529688B2 Phenolic compound and recording material 有权
标题翻译：酚类化合物和记录材料
公开(公告)号：US08529688B2
公开(公告)日：2013-09-10
申请号：US13138301
申请日：2010-02-01
申请人： Satoshi Kodama , Shinichi Satoh , Toshio Aihara , Tadashi Kawakami , Kazumi Jyujyo
发明人： Satoshi Kodama , Shinichi Satoh , Toshio Aihara , Tadashi Kawakami , Kazumi Jyujyo
IPC分类号： C09D7/12 , C07C235/38
CPC分类号： B41M5/3335 , B41M2205/28 , C07C233/29
摘要： Provided is a recording material with a superior storage property for the background and image, particularly with a remarkable superiority in any of light resistance of the background, and light, moisture and heat resistance of the image. The recording material contains a phenolic compound represented by formula (I) [wherein R1-R3 each independently represent a hydrogen atom or C1-C4 alkyl group; R5 represents a hydrogen atom, C1-C4 alkyl group or C1-C4 alkoxy group, with the proviso that when R5 is a hydrogen atom, R4 is a C1-C4 alkyl group, when R5 is a C1-C4 alkyl group, R4 is a hydrogen atom, and when R5 is a C1-C4 alkoxy group, R4 is a C1-C4 alkoxy group].
摘要翻译：提供了一种具有优异的背景和图像存储性能的记录材料，特别是在背景的任何耐光性以及图像的光，湿度和耐热性方面均显着优越。记录材料含有由式（I）表示的酚类化合物[其中R 1 -R 3各自独立地表示氢原子或C 1 -C 4烷基; R5表示氢原子，C1-C4烷基或C1-C4烷氧基，条件是当R5是氢原子时，R4是C1-C4烷基，当R5是C1-C4烷基时，R4是氢原子，当R5为C1-C4烷氧基时，R4为C1-C4烷氧基]。

3. 发明授权

US07696962B2 Color balancing circuit for a display panel 有权
标题翻译：显示面板的色彩平衡电路
公开(公告)号：US07696962B2
公开(公告)日：2010-04-13
申请号：US11127086
申请日：2005-05-12
申请人： Tetsuro Hara , Naoya Kimura , Takayuki Shimizu , Akira Kondo , Haruyo Takayanagi , Shinichi Satoh
发明人： Tetsuro Hara , Naoya Kimura , Takayuki Shimizu , Akira Kondo , Haruyo Takayanagi , Shinichi Satoh
IPC分类号： G09G5/10
CPC分类号： G09G3/3283 , G09G3/3216 , G09G2300/06 , G09G2320/0606 , G09G2320/0626 , G09G2320/0666
摘要： A color balancing circuit for a flat panel display such as an electroluminescent display generates a primary current that can be varied to adjust the overall brightness of the display. Three currents related to the primary current by selectable ratios are generated, by current mirror circuits, for example; the ratios can be individually varied to adjust the color balance. Driving currents are generated from the three adjusted currents, by mirroring the adjusted currents, for example, and are used to drive display elements that emit light in the three primary colors. Image brightness and color balance can accordingly be adjusted separately, even though both are adjusted by adjusting the driving current. Circuit size is reduced in that the same primary current is used for all three primary colors.
摘要翻译：用于诸如电致发光显示器的平板显示器的颜色平衡电路产生可以改变的初级电流以调节显示器的整体亮度。通过电流镜电路产生与初级电流相关的三个电流，例如：可以单独变化比例以调节颜色平衡。例如，通过镜像调节的电流，从三个调节的电流产生驱动电流，并且用于驱动以三原色发光的显示元件。因此，即使通过调节驱动电流来调整图像亮度和色彩平衡，也可以分别进行调整。电路尺寸减小，因为所有三原色使用相同的一次电流。

4. 发明授权

US07498867B2 Current drive circuit 失效
标题翻译：电流驱动电路
公开(公告)号：US07498867B2
公开(公告)日：2009-03-03
申请号：US11716651
申请日：2007-03-12
申请人： Shinichi Satoh
发明人： Shinichi Satoh
IPC分类号： G05F1/10
CPC分类号： H05B33/0827
摘要： In the current drive section, a wiring for setting a substrate potential is separately provided from a wiring of a power potential VDD so that substrate potentials of P-channel MOS transistors within respective drive cells become the same regardless of the distance from the power pad (power potential VDD) to each drive cell.
摘要翻译：在电流驱动部分中，用于设置衬底电位的布线从功率电位VDD的布线分开提供，使得各个驱动单元内的P沟道MOS晶体管的衬底电位与来自电源衬垫的距离成为相同电源电压VDD）。

5. 发明授权

US06249874B1 Information processing device 失效
标题翻译：信息处理装置
公开(公告)号：US06249874B1
公开(公告)日：2001-06-19
申请号：US08947158
申请日：1997-10-08
申请人： Isao Iwaguchi , Shinichi Satoh , Hiroaki Kawai , Mitsuo Watanabe , Motohiko Itoh
发明人： Isao Iwaguchi , Shinichi Satoh , Hiroaki Kawai , Mitsuo Watanabe , Motohiko Itoh
IPC分类号： G06F126
CPC分类号： G06F3/00 , G06F3/023
摘要： An information processing device connectable to another device via a transmission line includes an interface circuit connected to the transmission line, and a circuit which sends a signal to the transmission line and receive a signal from the transmission line. The interface circuit is supplied with electricity from the above another device. The above circuit is supplied with electricity from an external power source connected to the information processing device.
摘要翻译：经由传输线路连接到另一设备的信息处理设备包括连接到传输线路的接口电路，以及向传输线路发送信号并从传输线路接收信号的电路。接口电路由上述另一设备供电。上述电路由与信息处理装置连接的外部电源供电。

6. 发明授权

US5183774A Method of making a semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US5183774A
公开(公告)日：1993-02-02
申请号：US807659
申请日：1991-12-16
申请人： Shinichi Satoh
发明人： Shinichi Satoh
IPC分类号： H01L21/334 , H01L27/108
CPC分类号： H01L29/66181 , H01L27/10841
摘要： A semiconductor memory device comprises a semiconductor substrate (10), a trench (12) formed on a main surface (11) of the semiconductor substrate, a gate region (15) formed on a main surface portion in the trench, a passive element region (16) formed on a bottom side portion of the trench and a source/drain region (20) formed on the main surface of the semiconductor substrate. The method for manufacturing the semiconductor memory device comprises the steps of forming a wide first trench (31) on a portion of the main surface of the semiconductor substrate, forming a narrow second trench (32) on the bottom portion of the first trench, forming a passive element region in the second trench, forming a gate region in the first trench, and forming a source/drain region on the main surface portion of the semiconductor substrate.
摘要翻译：半导体存储器件包括半导体衬底（10），形成在半导体衬底的主表面（11）上的沟槽（12），形成在沟槽中的主表面部分上的栅极区域（15），无源元件区域（16），形成在所述沟槽的底侧部分上，以及形成在所述半导体衬底的主表面上的源/漏区（20）。半导体存储器件的制造方法包括以下步骤：在半导体衬底的主表面的一部分上形成宽的第一沟槽（31），在第一沟槽的底部形成窄的第二沟槽（32），形成在所述第二沟槽中的无源元件区域，在所述第一沟槽中形成栅极区域，以及在所述半导体衬底的所述主表面部分上形成源极/漏极区域。

7. 发明授权

US5101057A Fluorinated carboxylic acid derivatives and methods for making 失效
标题翻译：氟化羧酸衍生物及其制备方法
公开(公告)号：US5101057A
公开(公告)日：1992-03-31
申请号：US562320
申请日：1990-08-03
申请人： Shinichi Satoh , Noriyuki Koike , Hideki Fujii
发明人： Shinichi Satoh , Noriyuki Koike , Hideki Fujii
IPC分类号： B01J31/22 , C07B61/00 , C07F7/12 , C07F7/18
CPC分类号： C07F7/1896 , C07F7/182 , C07F7/1828 , C07F7/1836
摘要： Novel fluorinated carboxylic acid derivatives of the general formula: ##STR1## wherein R.sup.1 and R.sup.2 are independently selected from substituted or unsubstituted monovalent hydrocarbon groups, Rf is a divalent perfluoroalkyl or perfluoropolyether group, X is a hydrogen atom or triorganosilyl group, and a is equal to 2 or 3 are useful curing catalysts for RTV organopolysiloxane compositions. These fluorinated carboxylic acid derivatives are prepared by effecting hydrosilylation between alkenyl-containing fluorinated carboxylic acid derivatives and hydrosilanes in the presence of catalysts.
摘要翻译：新的具有以下通式的氟化羧酸衍生物：其中R 1和R 2独立地选自取代或未取代的一价烃基，R f是二价全氟烷基或全氟聚醚基团，X是氢原子或三有机甲硅烷基，和 a等于2或3是用于RTV有机聚硅氧烷组合物的有用固化催化剂。这些氟化羧酸衍生物通过在催化剂存在下进行含烯基的含氟羧酸衍生物和氢化硅烷之间的氢化硅烷化来制备。

8. 发明授权

US5097310A Complementary semiconductor device having improved device isolating region 失效
标题翻译：具有改进的器件隔离区域的补充半导体器件
公开(公告)号：US5097310A
公开(公告)日：1992-03-17
申请号：US409379
申请日：1989-09-19
申请人： Takahisa Eimori , Wataru Wakamiya , Hiroji Ozaki , Yoshinori Tanaka , Shinichi Satoh
发明人： Takahisa Eimori , Wataru Wakamiya , Hiroji Ozaki , Yoshinori Tanaka , Shinichi Satoh
IPC分类号： H01L21/761 , H01L21/76 , H01L27/08 , H01L27/092 , H01L29/78
CPC分类号： H01L27/0928
摘要： A complementary semiconductor device having an improved capability of isolating devices comprises a P well 3 and an N well 2 both formed adjacent to each other on a main surface of a substrate 1, an N type impurity layer formed in the P well 8 on the main surface of the substrate, a P type impurity layer formed in the N well 9 on the main surface of the substrate, an N type region formed at the junction of the N well and the P well 71 on the main surface of the substrate, a first shield electrode 52 formed between the N type impurity layer 8 and the N type region 71 on the main surface of the substrate through an insulating film and a second shield electrode 51 formed between the N type region 71 and the P type impurity layer 9 on the main surface of the substrate through an insulating film. The first shield electrode 52 is connected to a potential V.sub.SS and the second shield electrode 51 and the N type region 71 are connected to a potential V.sub.CC, so that an N channel MOS transistor 101 comprising the first shield electrode 52 does not turn on and a device comprising the second shield electrode does not form a field effect transistor.
摘要翻译：具有改进的隔离装置能力的互补半导体器件包括在衬底1的主表面上彼此相邻形成的P阱3和N阱2，形成在主衬底1上的P阱8中的N型杂质层在基板的主表面上形成在N阱9中的P型杂质层，形成在基板主表面上的N阱和P阱71的接合部的N型区域，第一屏蔽电极52，其通过绝缘膜形成在基板的主表面上的N型杂质层8和N型区域71之间，形成在N型区域71和P型杂质层9之间的第二屏蔽电极51，基板的主表面通过绝缘膜。第一屏蔽电极52连接到电位VSS，第二屏蔽电极51和N型区域71连接到电位VCC，使得包括第一屏蔽电极52的N沟道MOS晶体管101不导通，包括第二屏蔽电极的装置不形成场效应晶体管。

9. 发明授权

US5084752A Semiconductor device having bonding pad comprising buffer layer 失效
标题翻译：具有包含缓冲层的接合片的半导体器件
公开(公告)号：US5084752A
公开(公告)日：1992-01-28
申请号：US538817
申请日：1990-06-15
申请人： Shinichi Satoh , Hiroji Ozaki , Hiroshi Kimura , Wataru Wakamiya , Yoshinori Tanaka
发明人： Shinichi Satoh , Hiroji Ozaki , Hiroshi Kimura , Wataru Wakamiya , Yoshinori Tanaka
IPC分类号： H01L21/60 , H01L23/485
CPC分类号： H01L24/05 , H01L24/03 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/45124 , H01L2224/45144 , H01L2224/48247 , H01L2224/48463 , H01L2224/48624 , H01L2224/48644 , H01L2224/48724 , H01L2224/85205 , H01L24/45 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/01068 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/3025
摘要： A semiconductor device includes a substrate (4) in a periphery of which are formed elements isolating regions. A bonding pad (3) is formed above the elements isolating region, with an isolation layer (7) provided therebetween. An underlying layer (12) having a buffering function is formed on a surface of the bonding pad and the semiconductor substrate. In one aspect of the invention, wherein the elements isolating region is formed of LOCOS film (30), the underlying layer is formed between the bonding pad and the LOCOS film. In another aspect of the invention, the elements isolating region is of a field-shield structure (13, 14), and the underlying layer (12) is formed by separating a part of a gate electrode layer (14) of the field shield into an island. The underlying layer buffers the structure against an external force that is applied on the bonding pad in a bonding processing, to thereby prevent generation of cracks in the semiconductor layer.
摘要翻译：半导体器件包括其周边的衬底（4），其形成有元件隔离区域。在元件隔离区域的上方形成接合焊盘（3），其间设有隔离层（7）。在接合焊盘和半导体衬底的表面上形成具有缓冲功能的下层（12）。在本发明的一个方面，其中元件隔离区由LOCOS膜（30）形成，下层在接合焊盘和LOCOS膜之间形成。在本发明的另一方面，元件隔离区域是场屏蔽结构（13,14），并且下层（12）是通过将场屏蔽的栅极电极层（14）的一部分分成一个岛屿。底层在结合处理中抵抗施加在接合焊盘上的外力缓冲结构，从而防止在半导体层中产生裂纹。

10. 发明授权

US5027173A Semiconductor memory device with two separate gates per block 失效
标题翻译：半导体存储器件，每个块具有两个独立的栅极
公开(公告)号：US5027173A
公开(公告)日：1991-06-25
申请号：US261022
申请日：1988-10-20
申请人： Shinichi Satoh
发明人： Shinichi Satoh
IPC分类号： H01L27/10 , H01L21/334 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
CPC分类号： H01L29/66181 , H01L27/10841
摘要： A semiconductor memory device comprises a semiconductor substrate (10), a trench (12) formed on a main surface (11) of the semiconductor substrate, a gate region (15) formed on a main surface portion in the trench, a passive element region (16) formed on a bottom side portion of the trench and a source/drain region (20) formed on the main surface of the semiconductor substrate. The method for manufacturing the semiconductor memory device comprises the steps of forming a wide first trench (31) on a portion of the main surface of the semiconductor substrate, forming a narrow second trench (32) on the bottom portion of the first trench, forming a passive element region in the second trench, forming a gate region in the first trench, and forming a source/drain region on the main surface portion of the semiconductor substrate.
摘要翻译：半导体存储器件包括半导体衬底（10），形成在半导体衬底的主表面（11）上的沟槽（12），形成在沟槽中的主表面部分上的栅极区域（15），无源元件区域（16），形成在所述沟槽的底侧部分上，以及形成在所述半导体衬底的主表面上的源/漏区（20）。半导体存储器件的制造方法包括以下步骤：在半导体衬底的主表面的一部分上形成宽的第一沟槽（31），在第一沟槽的底部形成窄的第二沟槽（32），形成在所述第二沟槽中的无源元件区域，在所述第一沟槽中形成栅极区域，以及在所述半导体衬底的所述主表面部分上形成源极/漏极区域。

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