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    • 4. 发明授权
    • Frame synchronization apparatus
    • 帧同步装置
    • US5680421A
    • 1997-10-21
    • US604832
    • 1996-02-22
    • Haruhiro ShiinoNorio YamaguchiToshimichi NaoiRyoichi Miyamoto
    • Haruhiro ShiinoNorio YamaguchiToshimichi NaoiRyoichi Miyamoto
    • H04L7/04H04L7/08H04L7/00
    • H04L7/042H04L7/08
    • A frame synchronization apparatus is applied to the TDMA (Time Division Multiple Access) communication system, particularly, where a plurality of transmission rates are available. The frame synchronization apparatus calculates correlations between sampled sequences of a received signal and an assigned sync sequence during the longest or shortest frame period in the plurality of transmission rates. The apparatus stores positions where the correlations exceed a given threshold. Then, the apparatus sets a search gate at a position after a lapse of the longest or shortest frame period from each of those positions. The apparatus calculates correlations between the sync sequence and sampled sequences of the received signal for all the search gates. The actual transmission rate is determined from the plurality of transmission rates based on a time interval of positions where the correlations beyond a second threshold were detected. Synchronization is thus established.
    • 帧同步装置被应用于TDMA(时分多址)通信系统,特别是在多个传输速率可用的情况下。 帧同步装置在多个传输速率的最长或最短帧周期期间,计算接收信号的采样序列与分配的同步序列之间的相关性。 该装置存储相关性超过给定阈值的位置。 然后,该设备在从这些位置中的每个位置经过最长或最短帧周期之后的位置处设置搜索门。 该装置计算所有搜索门的同步序列和接收信号的采样序列之间的相关性。 基于检测到超过第二阈值的相关性的位置的时间间隔,从多个传输速率确定实际传输速率。 因此建立同步。
    • 5. 发明授权
    • Receiver for a digital communication system
    • 接收机用于数字通信系统
    • US5751776A
    • 1998-05-12
    • US736767
    • 1996-10-25
    • Haruhiro ShiinoNorio YamaguchiToshimichi Naoi
    • Haruhiro ShiinoNorio YamaguchiToshimichi Naoi
    • H04L7/04H04L27/00H04L27/227H04L7/02
    • H04L27/2273H04L2027/0028H04L2027/0067H04L2027/0069H04L7/042
    • A receiver to be employed in a digital mobile communication system, more particularly to a receiver for performing complex correlation against a received signal so as to establish and supervise the synchronization with the received signal. The receiver estimates a transmission channel between sending and receiving stations using the received signal and a predetermined reference signal (S11). The phase of the received signal is compensated for using the estimated phase error resulting from the estimation (S12). Complex correlation of the received signal which is compensated for in phase is performed against the reference signal (S13) to obtain a correlation value. The correlation value is compared with a predetermined threshold value (S14). The presence or absence of synchronization between the sending and receiving stations can be detected based on the result of the comparison. In case of detecting synchronization again after the synchronization is once detected, the phase of the received signal is compensated for (S22) using a previously obtained phase variation amount whereby the complex correlation value can be obtained (S23).
    • 一种在数字移动通信系统中使用的接收机,更具体地涉及一种用于对接收到的信号执行复杂相关以便建立并监督与接收信号的同步的接收机。 接收机使用接收到的信号和预定的参考信号来估计发送站和接收站之间的传输信道(S11)。 使用由估计得到的估计相位误差补偿接收信号的相位(S12)。 对参考信号(S13)进行相位补偿的接收信号的复相关,得到相关值。 将相关值与预定阈值进行比较(S14)。 可以基于比较的结果来检测发送站和接收站之间是否存在同步。 在一旦检测到同步之后再次检测同步的情况下,使用先前获得的相位变化量补偿接收信号的相位(S22),由此可以获得复相关值(S23)。
    • 7. 发明授权
    • Adaptive equalizer for controlling a step size in proportion to an
estimated delay of received signals
    • 自适应均衡器,用于与接收信号的估计延迟成比例地控制步长
    • US06021161A
    • 2000-02-01
    • US840638
    • 1997-04-25
    • Norio YamaguchiHaruhiro Shiino
    • Norio YamaguchiHaruhiro Shiino
    • H04B7/005H04L25/03H04L27/01
    • H04L25/03019
    • An adaptive equalizer increases the estimation accuracy of a channel, and prevents the modulation characteristics from degrading. A sampling circuit generates a sampled sequence from a received signal. The sampled sequence is supplied from a buffer to an equalizing circuit, a channel estimating circuit and a delay amount estimating circuit. The equalizing circuit obtains an estimated transmitted symbol sequence from the sampled sequence and an estimated impulse response sequence. The channel estimating circuit obtains the estimated impulse response sequence from the sampled sequence, estimated transmitted symbol sequence and the estimated error. The delay amount estimating circuit supplies an estimated delay amount to a step-size control circuit. An error extracting circuit obtains the estimated error. The step-size control circuit controls a step-size parameter in response to the delay amount, and a tap coefficient update circuit updates the tap coefficients by the estimated transmitted symbol, estimated error e.sub.n and step-size parameter.
    • 自适应均衡器增加了信道的估计精度,并且防止了调制特性的劣化。 采样电路从接收信号产生采样序列。 采样序列从缓冲器提供给均衡电路,信道估计电路和延迟量估计电路。 均衡电路从采样序列和估计的脉冲响应序列获得估计的发送符号序列。 信道估计电路从采样序列,估计发射符号序列和估计误差获得估计的脉冲响应序列。 延迟量估计电路向步长控制电路提供估计的延迟量。 误差提取电路获得估计误差。 步进大小控制电路响应于延迟量控制步长参数,并且抽头系数更新电路通过估计的发送符号,估计误差en和步长参数来更新抽头系数。