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1. 发明申请

US20050121704A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050121704A1
公开(公告)日：2005-06-09
申请号：US10983658
申请日：2004-11-09
申请人： Kenichi Tokano , Atsuko Yamashita , Koichi Takahashi , Hideki Okumura , Shingo Sato
发明人： Kenichi Tokano , Atsuko Yamashita , Koichi Takahashi , Hideki Okumura , Shingo Sato
IPC分类号： H01L21/764 , H01L21/265 , H01L21/336 , H01L21/76 , H01L29/06 , H01L29/76 , H01L29/78
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0653 , H01L29/66712
摘要： Provided is a semiconductor device including a semiconductor substrate which includes a first semiconductor layer of a first conductivity and a pair of second semiconductor layers disposed on the first semiconductor layer and spaced apart from each other to form a trench therebetween, wherein the second semiconductor layer includes a first impurity-diffused region of the first conductivity extending from a lower surface toward an upper surface of the second semiconductor layer, and a second impurity-diffused region of a second conductivity which extends from the lower surface toward the upper surface and is adjacent to the first impurity-diffused region, an insulating layer covering a sidewall of the trench, and a cap layer which is in contact with the semiconductor substrate and covers an opening of the trench to form an enclosed space in the trench, a material of the cap layer being almost the same as that of the semiconductor substrate.
摘要翻译：提供了一种半导体器件，其包括半导体衬底，该半导体衬底包括第一导电性的第一半导体层和设置在第一半导体层上并且彼此间隔开以在其间形成沟槽的一对第二半导体层，其中第二半导体层包括从第一半导体层的下表面向上表面延伸的第一导电性的第一杂质扩散区和从下表面向上表面延伸的第二导电性的第二杂质扩散区，第一杂质扩散区域，覆盖沟槽的侧壁的绝缘层，以及与半导体衬底接触并覆盖沟槽的开口以在沟槽中形成封闭空间的覆盖层，帽的材料层几乎与半导体衬底的层相同。

2. 发明申请

US20050006699A1 Semiconductor device and its manufacturing method 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20050006699A1
公开(公告)日：2005-01-13
申请号：US10844323
申请日：2004-05-13
申请人： Shingo Sato , Atsuko Yamashita , Hideki Okumura , Kenichi Tokano
发明人： Shingo Sato , Atsuko Yamashita , Hideki Okumura , Kenichi Tokano
IPC分类号： H01L21/336 , H01L29/06 , H01L29/10 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/66712
摘要： A semiconductor device comprises: a semiconductor layer of a first conductivity type; a first semiconductor pillar layer of the first conductivity type; a second semiconductor pillar layer of a second conductivity type; a third semiconductor pillar layer of the first conductivity type; a forth semiconductor pillar layer of the second conductivity type; a fifth semiconductor pillar layer of the first conductivity type provided on the major surface of the semiconductor layer; a first semiconductor base layer of the second conductivity type provided on the second semiconductor pillar layer; a second semiconductor base layer of the second conductivity type provided on the forth semiconductor pillar layer; first semiconductor region of the first conductivity type selectively provided on a surface of the first semiconductor base layer; second semiconductor region of the first conductivity type selectively provided on a surface of the second semiconductor base layer; gate insulating film provided on the first semiconductor base layer between the first semiconductor region and the first semiconductor pillar layer and between the first semiconductor region and the third semiconductor pillar layer, and provided on the second semiconductor base layer between the second semiconductor region and the third semiconductor pillar layer and between the second semiconductor region and the fifth semiconductor pillar layer; and gate electrode provided on the gate insulating film. Each width of the first through fifth semiconductor pillar layers seen in a perpendicular direction to interfaces of p-n junctions formed among the first through fifth semiconductor pillar layers respectively is 10 microns or less.
摘要翻译：半导体器件包括：第一导电类型的半导体层; 第一导电类型的第一半导体柱层; 第二导电类型的第二半导体柱层; 第一导电类型的第三半导体柱层; 第二导电类型的第四半导体柱层; 设置在半导体层的主表面上的第一导电类型的第五半导体柱层; 设置在第二半导体柱层上的第二导电类型的第一半导体基底层; 设置在第四半导体柱层上的第二导电类型的第二半导体基底层; 选择性地设置在第一半导体基底层的表面上的第一导电类型的第一半导体区域; 选择性地设置在第二半导体基底层的表面上的第一导电类型的第二半导体区域; 栅极绝缘膜，设置在第一半导体基底层之间的第一半导体区域和第一半导体柱层之间以及第一半导体区域和第三半导体柱层之间，并且设置在第二半导体基底层上的第二半导体区域和第三半导体区域之间半导体柱层和第二半导体区域和第五半导体柱层之间; 以及设置在栅极绝缘膜上的栅电极。在与第一至第五半导体柱层之间形成的p-n结的界面的垂直方向上分别看到的第一至第五半导体柱层的宽度分别为10微米以下。

3. 发明授权

US07391077B2 Vertical type semiconductor device 失效
标题翻译：垂直型半导体器件
公开(公告)号：US07391077B2
公开(公告)日：2008-06-24
申请号：US10983658
申请日：2004-11-09
申请人： Kenichi Tokano , Atsuko Yamashita , Koichi Takahashi , Hideki Okumura , Shingo Sato
发明人： Kenichi Tokano , Atsuko Yamashita , Koichi Takahashi , Hideki Okumura , Shingo Sato
IPC分类号： H01L21/764
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0653 , H01L29/66712
摘要： Provided is a semiconductor device including a semiconductor substrate which includes a first semiconductor layer of a first conductivity and a pair of second semiconductor layers disposed on the first semiconductor layer and spaced apart from each other to form a trench therebetween, wherein the second semiconductor layer includes a first impurity-diffused region of the first conductivity extending from a lower surface toward an upper surface of the second semiconductor layer, and a second impurity-diffused region of a second conductivity which extends from the lower surface toward the upper surface and is adjacent to the first impurity-diffused region, an insulating layer covering a sidewall of the trench, and a cap layer which is in contact with the semiconductor substrate and covers an opening of the trench to form an enclosed space in the trench, a material of the cap layer being almost the same as that of the semiconductor substrate.
摘要翻译：提供了一种半导体器件，其包括半导体衬底，该半导体衬底包括第一导电性的第一半导体层和设置在第一半导体层上并且彼此间隔开以在其间形成沟槽的一对第二半导体层，其中第二半导体层包括从第一半导体层的下表面向上表面延伸的第一导电性的第一杂质扩散区和从下表面向上表面延伸的第二导电性的第二杂质扩散区，第一杂质扩散区域，覆盖沟槽的侧壁的绝缘层，以及与半导体衬底接触并覆盖沟槽的开口以在沟槽中形成封闭空间的覆盖层，帽的材料层几乎与半导体衬底的层相同。

4. 发明授权

US07075149B2 Semiconductor device and its manufacturing method 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US07075149B2
公开(公告)日：2006-07-11
申请号：US10844323
申请日：2004-05-13
申请人： Shingo Sato , Atsuko Yamashita , Hideki Okumura , Kenichi Tokano
发明人： Shingo Sato , Atsuko Yamashita , Hideki Okumura , Kenichi Tokano
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/66712
摘要： A semiconductor device comprises: a semiconductor layer of a first conductivity type; a first semiconductor pillar layer of the first conductivity type; a second semiconductor pillar layer of a second conductivity type; a third semiconductor pillar layer of the first conductivity type; a forth semiconductor pillar layer of the second conductivity type; a fifth semiconductor pillar layer of the first conductivity type provided on the major surface of the semiconductor layer; a first semiconductor base layer of the second conductivity type provided on the second semiconductor pillar layer; a second semiconductor base layer of the second conductivity type provided on the forth semiconductor pillar layer; first semiconductor region of the first conductivity type selectively provided on a surface of the first semiconductor base layer; second semiconductor region of the first conductivity type selectively provided on a surface of the second semiconductor base layer; gate insulating film provided on the first semiconductor base layer between the first semiconductor region and the first semiconductor pillar layer and between the first semiconductor region and the third semiconductor pillar layer, and provided on the second semiconductor base layer between the second semiconductor region and the third semiconductor pillar layer and between the second semiconductor region and the fifth semiconductor pillar layer; and gate electrode provided on the gate insulating film. Each width of the first through fifth semiconductor pillar layers seen in a perpendicular direction to interfaces of p-n junctions formed among the first through fifth semiconductor pillar layers respectively is 10 microns or less.
摘要翻译：半导体器件包括：第一导电类型的半导体层; 第一导电类型的第一半导体柱层; 第二导电类型的第二半导体柱层; 第一导电类型的第三半导体柱层; 第二导电类型的第四半导体柱层; 设置在半导体层的主表面上的第一导电类型的第五半导体柱层; 设置在第二半导体柱层上的第二导电类型的第一半导体基底层; 设置在第四半导体柱层上的第二导电类型的第二半导体基底层; 选择性地设置在第一半导体基底层的表面上的第一导电类型的第一半导体区域; 选择性地设置在第二半导体基底层的表面上的第一导电类型的第二半导体区域; 栅极绝缘膜，设置在第一半导体基底层之间的第一半导体区域和第一半导体柱层之间以及第一半导体区域和第三半导体柱层之间，并且设置在第二半导体基底层上的第二半导体区域和第三半导体区域之间半导体柱层和第二半导体区域和第五半导体柱层之间; 以及设置在栅极绝缘膜上的栅电极。在与第一至第五半导体柱层之间形成的p-n结的界面的垂直方向上分别看到的第一至第五半导体柱层的宽度分别为10微米以下。

5. 发明申请

US20060043480A1 Semiconductor device and fabrication method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20060043480A1
公开(公告)日：2006-03-02
申请号：US10991433
申请日：2004-11-19
申请人： Masanobu Tsuchitani , Tetsuo Matsuda , Hideki Okumura , Atsuko Yamashita
发明人： Masanobu Tsuchitani , Tetsuo Matsuda , Hideki Okumura , Atsuko Yamashita
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/66712 , H01L29/0619 , H01L29/0634 , H01L29/42368 , H01L29/7811
摘要： A semiconductor device comprises a semiconductor layer which includes a terminate end part and a cell formation part that is surrounded by this end part, and a plurality of guard rings each of which is formed at the end part to surround the cell formation part. These guard rings are made shallower and smaller in width as they get near to the guard ring that resides at the outside position.
摘要翻译：半导体器件包括半导体层，其包括终端部分和由该端部部分包围的电池形成部分，以及多个保护环，每个保护环形成在端部处以围绕电池形成部分。这些保护环的宽度越来越小，因为它们靠近位于外部位置的防护环。

6. 发明授权

US07420245B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07420245B2
公开(公告)日：2008-09-02
申请号：US11194609
申请日：2005-08-02
申请人： Atsuko Yamashita , Tetsuo Matsuda , Hideki Okumura , Masanobu Tsuchitani
发明人： Atsuko Yamashita , Tetsuo Matsuda , Hideki Okumura , Masanobu Tsuchitani
IPC分类号： H01L29/94
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/66712
摘要： A first semiconductor pillar layer of a first conductivity type is formed on a main surface of a semiconductor substrate of the first conductivity type. A second semiconductor pillar layer of a second conductivity type is formed adjacent to the first semiconductor pillar layer. A third semiconductor pillar layer of the first conductivity type is formed adjacent to the second semiconductor pillar layer. A semiconductor base layer of the second conductivity type is formed on the main surface of the second semiconductor pillar layer. An insulated-gate type semiconductor element is formed in the semiconductor base layer. The carrier concentration on the side of a main surface of each of said first through third semiconductor pillar layers is higher than a carrier concentration on the opposite side of said main surface in each of said first through third semiconductor pillar layers.
摘要翻译：第一导电类型的第一半导体柱层形成在第一导电类型的半导体衬底的主表面上。形成与第一半导体柱层相邻的第二导电类型的第二半导体柱层。形成与第二半导体柱层相邻的第一导电类型的第三半导体柱层。第二导电类型的半导体基底层形成在第二半导体柱层的主表面上。在半导体基底层中形成绝缘栅型半导体元件。所述第一〜第三半导体柱层的主表面侧的载流子浓度高于所述第一〜第三半导体柱层的所述主面的相对侧的载流子浓度。

7. 发明申请

US20060043481A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060043481A1
公开(公告)日：2006-03-02
申请号：US11194609
申请日：2005-08-02
申请人： Atsuko Yamashita , Tetsuo Matsuda , Hideki Okumura , Masanobu Tsuchitani
发明人： Atsuko Yamashita , Tetsuo Matsuda , Hideki Okumura , Masanobu Tsuchitani
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/66712
摘要： A first semiconductor pillar layer of a first conductivity type is formed on a main surface of a semiconductor substrate of the first conductivity type. A second semiconductor pillar layer of a second conductivity type is formed adjacent to the first semiconductor pillar layer. A third semiconductor pillar layer of the first conductivity type is formed adjacent to the second semiconductor pillar layer. A semiconductor base layer of the second conductivity type is formed on the main surface of the second semiconductor pillar layer. An insulated-gate type semiconductor element is formed in the semiconductor base layer. The carrier concentration on the side of a main surface of each of said first through third semiconductor pillar layers is higher than a carrier concentration on the opposite side of said main surface in each of said first through third semiconductor pillar layers.
摘要翻译：第一导电类型的第一半导体柱层形成在第一导电类型的半导体衬底的主表面上。形成与第一半导体柱层相邻的第二导电类型的第二半导体柱层。形成与第二半导体柱层相邻的第一导电类型的第三半导体柱层。第二导电类型的半导体基底层形成在第二半导体柱层的主表面上。在半导体基底层中形成绝缘栅型半导体元件。所述第一〜第三半导体柱层的主表面侧的载流子浓度高于所述第一〜第三半导体柱层的所述主面的相对侧的载流子浓度。

8. 发明申请

US20090096051A1 SOLID STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING SAME, AND SOLID STATE IMAGING MODULE 有权
标题翻译：固态成像装置及其制造方法和固态成像模块
公开(公告)号：US20090096051A1
公开(公告)日：2009-04-16
申请号：US12249438
申请日：2008-10-10
申请人： Hitoshi SUGIYAMA , Atsuko Yamashita , Kazutaka Akiyama , Susumu Harada , Masahiro Sekiguchi , Masayuki Dohi , Kazumasa Tanida , Chiaki Takubo , Hiroshi Yoshikawa , Akihiro Hori
发明人： Hitoshi SUGIYAMA , Atsuko Yamashita , Kazutaka Akiyama , Susumu Harada , Masahiro Sekiguchi , Masayuki Dohi , Kazumasa Tanida , Chiaki Takubo , Hiroshi Yoshikawa , Akihiro Hori
IPC分类号： H01L31/0216 , H01L31/18
CPC分类号： H01L27/14634 , H01L27/14618 , H01L27/14623 , H01L27/14636 , H01L27/14685 , H01L2224/05001 , H01L2224/05009 , H01L2224/05022 , H01L2224/05025 , H01L2224/05147 , H01L2224/0557 , H01L2224/05624 , H01L2224/05666 , H01L2224/05684 , H01L2224/13 , H01L2224/13025 , H01L2224/16 , H01L2924/00014
摘要： A solid state imaging device includes: an imaging device substrate with an imaging device section formed on a first major surface side thereof; a backside interconnect electrode provided on a second major surface side of the imaging device substrate and electrically connected to the imaging device section, the second major surface being on the opposite side of the first major surface; a circuit substrate provided with a circuit substrate electrode opposed to the second major surface; a connecting portion electrically connecting the backside interconnect electrode to the circuit substrate electrode; and a light shielding layer provided coplanar with the backside interconnect electrode or on the circuit substrate side of the backside interconnect electrode.
摘要翻译：固态成像装置包括：具有形成在其第一主表面侧的成像装置部分的成像装置基板; 设置在成像器件基板的第二主表面侧并电连接到成像器件部分的背面互连电极，第二主表面在第一主表面的相对侧上; 电路基板，设置有与第二主表面相对的电路基板电极; 连接部，其将所述背面侧配线电极与所述电路基板电极电连接; 以及与背面配线电极共同设置的遮光层，或背面配线电极的电路基板侧。

9. 发明申请

US20080164527A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080164527A1
公开(公告)日：2008-07-10
申请号：US11955998
申请日：2007-12-13
申请人： Takashi Kataoka , Atsuko Yamashita , Yoshiharu Kouji
发明人： Takashi Kataoka , Atsuko Yamashita , Yoshiharu Kouji
IPC分类号： H01L23/62 , H01L21/3205
CPC分类号： H01L29/7787 , H01L29/155 , H01L29/2003 , H01L29/42316 , H01L29/4236
摘要： The semiconductor comprises a channel layer including GaN, a barrier layer formed by laminating a first layer including AlXGa1-XN (0.05≦X≦0.25) and a second layer including AlYGa1-YN (0.20≦Y≦0.28, X
摘要翻译：半导体包括沟道层，其包括GaN，通过层叠包含Al x Ga 1-X N（0.05 <= X <= 0.25）的第一层和包括Al Y Y 1 Y Y（0.20 <= Y <= 0.28，X

10. 发明授权

US06623542B2 Slide member 失效
公开(公告)号：US06623542B2
公开(公告)日：2003-09-23
申请号：US09983226
申请日：2001-10-23
申请人： Atsuko Yamashita , Yoshinori Itou , Fuminori Satoji
发明人： Atsuko Yamashita , Yoshinori Itou , Fuminori Satoji
IPC分类号： B22F310
CPC分类号： C22C32/0094 , F16C33/04
摘要： The slide member 5 slidably guided on the outer peripheral surface of a shaft is formed by adding 10-50% by volume of thermosetting resin to a metal powder consisting mainly of copper powder, iron powder or a mixture thereof and sintering the same at temperatures not less than the sintering temperature of the metal powder.

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