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1. 发明授权

US09412473B2 System and method of a novel redundancy scheme for OTP 有权
公开(公告)号：US09412473B2
公开(公告)日：2016-08-09
申请号：US14545775
申请日：2015-06-16
申请人： Shine C. Chung
发明人： Shine C. Chung
IPC分类号： G11C29/04 , G11C29/00 , G11C17/16 , G11C17/18
CPC分类号： G11C29/78 , G11C17/16 , G11C17/18 , G11C29/702
摘要： A novel redundancy scheme to repair no more than one defect per I/O in a One-Time-Programmable (OTP) memory is disclosed. An OTP memory has a plurality of OTP cells in a plurality of I/Os and at least one auxiliary OTP cell associated with each I/O. At least one volatile cell in each I/O corresponds to the auxiliary OTP cells. At least one Boolean gate to invert the data into and/or out of the main OTP memory in each I/O independently based on the data in the volatile cells. The data in each I/O of the OTP memory can be inverted if no more than one defect per I/O is found. Furthermore, the inversion scheme can be achieved by reading the auxiliary OTP cells and storing into the volatile cells by automatically generating at least one read cycle upon initialization.

2. 发明授权

US09349773B2 Memory devices using a plurality of diodes as program selectors for memory cells 有权
标题翻译：使用多个二极管作为存储器单元的程序选择器的存储器件
公开(公告)号：US09349773B2
公开(公告)日：2016-05-24
申请号：US13026783
申请日：2011-02-14
申请人： Shine C. Chung
发明人： Shine C. Chung
IPC分类号： H01L27/24 , G11C11/16 , G11C13/00 , G11C17/16 , H01L27/22 , H01L29/78 , H01L45/00
CPC分类号： H01L27/2436 , G11C8/14 , G11C11/1659 , G11C11/1675 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C17/16 , G11C17/165 , G11C2013/0073 , G11C2213/72 , G11C2213/74 , H01L27/224 , H01L27/2409 , H01L29/785 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/144 , H01L45/146
摘要： At least one junction diode fabricated in standard CMOS logic processes can be used as program selectors for the memory cells that can be programmed based on the directions of current flow. These memory cells are MRAM, RRAM, CBRAM, or other memory cells that have a resistive element coupled to the P terminal of the first diode and to the N terminal of a second diode. The diodes can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diodes. By applying a high voltage to a resistive element and switching the N terminal of the first diode to a low voltage while disabling the second diode, a current flows through the memory cell can change the resistance into one state. Similarly, by applying a low voltage to a resistive element and switching the P terminal of the second diode to a high voltage while disabling the first diode, a current flows through the memory cell can change the resistance into another state. The P+ active region of the diode can be isolated from the N+ active region in an N well by using dummy MOS gate, SBL, or STI isolations.
摘要翻译：以标准CMOS逻辑工艺制造的至少一个结二极管可用作可根据电流方向编程的存储器单元的程序选择器。这些存储单元是具有耦合到第一二极管的P端和第二二极管的N端的电阻元件的MRAM，RRAM，CBRAM或其它存储单元。二极管可以由N阱上的P +和N +有源区域构成，作为二极管的P和N端子。通过向电阻元件施加高电压并且在禁用第二二极管的同时将第一二极管的N端切换到低电压，流过存储器单元的电流可以将电阻改变成一个状态。类似地，通过对电阻元件施加低电压并且在禁用第一二极管的同时将第二二极管的P端子切换到高电压，流过存储器单元的电流可将电阻改变为另一状态。通过使用虚拟MOS栅极，SBL或STI隔离，二极管的P +有源区可以与N阱中的N +有源区隔离。

3. 发明授权

US09293220B2 Low-pin-count non-volatile memory interface for 3D IC 有权
标题翻译： 3D IC的低引脚数非易失性存储器接口
公开(公告)号：US09293220B2
公开(公告)日：2016-03-22
申请号：US14636155
申请日：2015-03-02
申请人： Shine C. Chung
发明人： Shine C. Chung
IPC分类号： G11C17/18 , G11C17/16 , G11C29/00 , G11C8/18 , G11C16/10 , G11C29/02 , G11C16/16 , G11C16/26 , G11C16/32 , G11C29/44
CPC分类号： G11C17/16 , G11C8/18 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/32 , G11C29/028 , G11C29/78 , G11C2029/4402 , G11C2216/30
摘要： A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit for a 3D IC to repair defects, trim devices, or adjust parameters is presented here. At least one die in a 3D IC can be built with at least one low-pin-count OTP memory. The low-pin-count OTP memory can be built with a serial interface such as I2C-like or SPI-like of interface. The pins of the low-pin-count OTP in at least one die can be coupled together to have only one set of low-pin-count bus for external access. With proper device ID, each die in a 3D IC can be accessed individually for soft programming, programming, erasing, or reading. This technique can improve the manufacture yield, device, circuit, or logic performance or to store configuration parameters for customization after 3D IC are built.
摘要翻译：这里介绍了在用于3D IC的集成电路中提供的用于修复缺陷，修整装置或调整参数的低引脚数非易失性（NVM）存储器。至少可以使用至少一个低引脚数OTP内存来构建3D IC中的至少一个裸片。低引脚数OTP存储器可以使用类似I2C或类似接口的串行接口来构建。至少一个管芯中的低引脚数OTP的引脚可以耦合在一起，以便只有一组低引脚数总线用于外部访问。通过适当的器件ID，可以单独访问3D IC中的每个管芯，以进行软编程，编程，擦除或读取。该技术可以提高制造产量，器件，电路或逻辑性能，或者在构建3D IC后存储用于定制的配置参数。

4. 发明授权

US09251893B2 Multiple-bit programmable resistive memory using diode as program selector 有权
标题翻译：使用二极管作为程序选择器的多位可编程电阻存储器
公开(公告)号：US09251893B2
公开(公告)日：2016-02-02
申请号：US13590044
申请日：2012-08-20
申请人： Shine C. Chung
发明人： Shine C. Chung
IPC分类号： G11C11/00 , G11C11/56 , G11C13/00
CPC分类号： G11C11/5678 , G11C11/5685 , G11C11/5692 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C13/0038 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2013/0073 , G11C2013/0092 , G11C2213/72 , G11C2213/74
摘要： A method and system for multiple-bit programmable resistive cells having a multiple-bit programmable resistive element and using diode as program selector are disclosed. The first and second terminals of the diode having a first and second types of dopants can be fabricated from source/drain of MOS in a well for MOS devices or fabricated on the same polysilicon structure. If a multiple-bit programmable resistive cell has 2n (n>1) distinct resistance levels to store n-bit data, at least 2n−1 reference resistance levels can be designated to differential resistances between two adjacent states. Programming multiple-bit programmable resistive elements can start by applying a program pulse with initial program voltage (or current) and duration. A read verification cycle can follow to determine if the desirable resistance level is reached. If the desired resistance level has not been reached, additional program pulses can be applied.
摘要翻译：公开了一种具有多位可编程电阻元件并使用二极管作为程序选择器的多位可编程电阻单元的方法和系统。具有第一和第二类掺杂剂的二极管的第一和第二端可以由用于MOS器件的阱中的MOS的源极/漏极制造或者制造在相同的多晶硅结构上。如果多位可编程电阻单元具有2n（n> 1）个不同的电阻电平来存储n位数据，则可以将至少2n-1个参考电阻电平指定为两个相邻状态之间的差分电阻。编程多位可编程电阻元件可以通过应用具有初始编程电压（或电流）和持续时间的编程脉冲来启动。可以遵循读取验证周期来确定是否达到所需的电阻值。如果尚未达到所需的电阻值，则可以应用附加的编程脉冲。

5. 发明授权

US09224496B2 Circuit and system of aggregated area anti-fuse in CMOS processes 有权
标题翻译： CMOS工艺中聚集区域反熔丝的电路和系统
公开(公告)号：US09224496B2
公开(公告)日：2015-12-29
申请号：US13072783
申请日：2011-03-28
申请人： Shine C. Chung
发明人： Shine C. Chung
IPC分类号： G11C17/00 , G11C11/00 , G11C17/12 , H01L27/06 , H01L23/525 , H01L27/10 , H01L29/10 , H01L29/78
CPC分类号： G11C17/12 , H01L23/5252 , H01L27/0629 , H01L27/101 , H01L29/1083 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： Gate oxide breakdown anti-fuse suffers notorious soft breakdown that reduces yield and reliability. This invention discloses circuit and system to enhance electrical field by blocking LDD so that the electrical field is higher and more focused near the drain junction, to make electrical field in the channel more uniform by creating slight conductive or conductive in part or all of the channel, or to neutralize excess carriers piled up in the oxide by applying alternative polarity pulses. The embodiments can be applied in part, all, or any combinations, depending on needs. This invention can be embodied as a 2 T anti-fuse cell having an access and a program MOS with drain area in the program MOS, or 1.5 T anti-fuse cell without any drain in the program MOS. Similarly this invention can also be embodied as a 1 T anti-fuse cell having a portion of the channel made conductive or slightly conductive to merge the access and program MOS into one device with drain area, or 0.5 T anti-fuse cell without any drain.
摘要翻译：栅极氧化物击穿抗熔丝遭受臭名昭着的软击穿，从而降低产量和可靠性。本发明公开了通过阻挡LDD来增强电场的电路和系统，使得电场在漏极结附近更高和更集中，以通过在部分或全部通道中产生轻微的导电或导电来使通道中的电场更均匀或通过施加替代的极性脉冲来中和堆积在氧化物中的过量载体。可以根据需要部分，全部或任何组合应用实施例。本发明可以实现为具有访问的2T反熔丝单元和在编程MOS中具有漏极区的编程MOS或在程序MOS中没有任何漏极的1.5T反熔丝单元。类似地，本发明也可以被实施为具有通道的一部分导通或稍微导电的1T反熔丝电池，以将访问和编程MOS合并成具有漏极区的一个器件，或没有任何漏极的0.5T反熔丝电池。

6. 发明申请

US20150187431A1 ONE-TIME PROGRAMMABLE MEMORY DEVICES USING FinFET TECHNOLOGY 有权
标题翻译：一次性可编程存储器件使用FinFET技术
公开(公告)号：US20150187431A1
公开(公告)日：2015-07-02
申请号：US14644020
申请日：2015-03-10
申请人： Shine C. Chung
发明人： Shine C. Chung
IPC分类号： G11C17/16 , G11C17/18
CPC分类号： G11C17/18 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/003 , G11C13/0038 , G11C13/004 , G11C17/06 , G11C17/16 , G11C17/165 , G11C2013/0054 , G11C2213/72 , G11C2213/74 , H01L23/5256 , H01L27/1021 , H01L27/11206 , H01L29/0649 , H01L29/66128 , H01L29/66136 , H01L29/732 , H01L29/785 , H01L29/861 , H01L29/8611 , H01L2924/0002 , H01L2924/00
摘要： An OTP (One-Time Programmable) element can be fabricated in CMOS FinFET processes are disclosed. The OTP cell can be implemented as a MOS device, dummy-gate diode, or Schottky diode as selector is disclosed here. In one embodiment, the OTP element includes a MOS gate with at least one portion of the MOS gate can have at least one extended area to accelerate programming. An extended area is an extension of the OTP element beyond two nearest cathode and anode contacts and are longer than required by design rules. The extended area can also have reduced or substantially no current flowing through. The selector can be built with a MOS gate to divide at least one fin structure into two different active regions. By using different source/drain implant schemes on the two active regions, the selector can be turned on as MOS device, MOS device and/or diode, dummy-gate diode, or Schottky diode.
摘要翻译：可以在CMOS FinFET工艺中制造OTP（一次可编程）元件。 OTP单元可以实现为MOS器件，伪栅极二极管或肖特基二极管，因为这里公开了选择器。在一个实施例中，OTP元件包括MOS栅极，MOS栅极的至少一部分可以具有至少一个扩展区域以加速编程。扩展区域是超出两个最近的阴极和阳极触点的OTP元件的延伸，并且比设计规则要求的长。扩展区域也可以减少或基本上没有电流流过。选择器可以用MOS栅极构建，以将至少一个鳍结构分成两个不同的有源区域。通过在两个有源区域上使用不同的源极/漏极注入方案，选择器可以作为MOS器件，MOS器件和/或二极管，伪栅极二极管或肖特基二极管导通。

7. 发明申请

US20150170759A1 Low-Pin-Count Non-Volatile Memory Interface for 3D IC 有权
标题翻译： 3D IC的低引脚数非易失性存储器接口
公开(公告)号：US20150170759A1
公开(公告)日：2015-06-18
申请号：US14636155
申请日：2015-03-02
申请人： Shine C. Chung
发明人： Shine C. Chung
IPC分类号： G11C17/16
CPC分类号： G11C17/16 , G11C8/18 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/32 , G11C29/028 , G11C29/78 , G11C2029/4402 , G11C2216/30
摘要： A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit for a 3D IC to repair defects, trim devices, or adjust parameters is presented here. At least one die in a 3D IC can be built with at least one low-pin-count OTP memory. The low-pin-count OTP memory can be built with a serial interface such as I2C-like or SPI-like of interface. The pins of the low-pin-count OTP in at least one die can be coupled together to have only one set of low-pin-count bus for external access. With proper device ID, each die in a 3D IC can be accessed individually for soft programming, programming, erasing, or reading. This technique can improve the manufacture yield, device, circuit, or logic performance or to store configuration parameters for customization after 3D IC are built.
摘要翻译：这里介绍了在用于3D IC的集成电路中提供的用于修复缺陷，修整装置或调整参数的低引脚数非易失性（NVM）存储器。至少可以使用至少一个低引脚数OTP内存来构建3D IC中的至少一个裸片。低引脚数OTP存储器可以使用类似I2C或类似接口的串行接口来构建。至少一个管芯中的低引脚数OTP的引脚可以耦合在一起，以便只有一组用于外部访问的低引脚数总线。通过适当的器件ID，可以单独访问3D IC中的每个管芯，以进行软编程，编程，擦除或读取。该技术可以提高制造产量，器件，电路或逻辑性能，或者在构建3D IC后存储用于定制的配置参数。

8. 发明授权

US08988965B2 Low-pin-count non-volatile memory interface 有权
标题翻译：低引脚数非易失性存储器接口
公开(公告)号：US08988965B2
公开(公告)日：2015-03-24
申请号：US13288843
申请日：2011-11-03
申请人： Shine C. Chung
发明人： Shine C. Chung
IPC分类号： G11C17/18
CPC分类号： G11C8/18 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/32 , G11C17/00 , G11C2216/30
摘要： A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit. In one embodiment, the low-pin-count non-volatile (NVM) memory can use only one external control signal and one internal clock signal to generate start, stop, device ID, read/program/erase pattern, starting address, and actual read/program/erase cycles. When programming or erasing begins, toggling of the control signal increments/decrements a program or erase address and a pulse width of the control signal determines the actual program or erase time. A data out of the low-pin-count non-volatile (NVM) memory can be multiplexed with the control signal. Since the clock signal can be derived and shared from the system clock of the integrated circuit, the NVM memory need only have one external control pin for I/O transactions to realize a low-pin-count interface.
摘要翻译：在集成电路中提供的低引脚数非易失性（NVM）存储器。在一个实施例中，低引脚数非易失性（NVM）存储器可以仅使用一个外部控制信号和一个内部时钟信号来产生启动，停止，器件ID，读/写/擦除模式，起始地址和实际读/写/擦除周期。当编程或擦除开始时，控制信号的切换递增/递减编程或擦除地址，并且控制信号的脉冲宽度决定实际的编程或擦除时间。低引脚数非易失性（NVM）存储器中的数据可以与控制信号复用。由于可以从集成电路的系统时钟导出和共享时钟信号，所以NVM存储器只需要一个用于I / O事务的外部控制引脚来实现低引脚数接口。

9. 发明申请

US20150021543A1 Programmably Reversible Resistive Device Cells Using CMOS Logic Processes 有权
标题翻译：使用CMOS逻辑过程可编程的可逆电阻器件单元
公开(公告)号：US20150021543A1
公开(公告)日：2015-01-22
申请号：US14507691
申请日：2014-10-06
申请人： Shine C. Chung
发明人： Shine C. Chung
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/2436 , G11C8/14 , G11C11/1659 , G11C11/1675 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C17/16 , G11C17/165 , G11C2013/0073 , G11C2213/72 , G11C2213/74 , H01L27/224 , H01L27/2409 , H01L29/785 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/144 , H01L45/146
摘要： Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive devices, such as PCM, RRAM, CBRAM, or other memory cells. The reversible resistive devices have a reversible resistive element coupled to a diode. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a voltage or a current between a reversible resistive element and the N terminal of a diode, the reversible resistive device can be programmed into different states based on magnitude, duration, voltage-limit, or current-limit in a reversible manner. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations.
摘要翻译：以标准CMOS逻辑处理器制造的结二极管可用作可逆电阻器件（如PCM，RRAM，CBRAM或其他存储器单元）的程序选择器。可逆电阻器件具有耦合到二极管的可逆电阻元件。二极管可以由N阱上的P +和N +有源区构成，作为二极管的P和N端。通过在可逆电阻元件和二极管的N端之间施加电压或电流，可逆电阻器件可以以可逆的方式基于幅度，持续时间，电压限制或电流限制被编程到不同的状态。通过使用虚拟MOS栅极，SBL或STI / LOCOS隔离，二极管的P +有源区可以与N阱中的N +有源区隔离。

10. 发明授权

US08913449B2 System and method of in-system repairs or configurations for memories 有权
标题翻译：系统和系统内修复方法或存储器配置
公开(公告)号：US08913449B2
公开(公告)日：2014-12-16
申请号：US13571797
申请日：2012-08-10
申请人： Shine C. Chung
发明人： Shine C. Chung
IPC分类号： G11C29/00
CPC分类号： G11C17/18 , G11C17/16 , G11C29/785
摘要： In-system repairing or configuring faulty memories after being used in a system. In one embodiment, a memory chip can include at least one OTP memory to store defective addresses that are to be repaired. The OTP memory can operate without requiring additional I/O pins or high voltage supplies for reading or programming. The memory chip can also include control logic to control reading or programming of the OTP memory as needed.
摘要翻译：在系统中使用系统后修复或配置故障存储器。在一个实施例中，存储器芯片可以包括至少一个OTP存储器来存储待修复的缺陷地址。 OTP存储器可以工作，无需额外的I / O引脚或高电压电源进行读取或编程。存储器芯片还可以包括用于根据需要控制OTP存储器的读取或编程的控制逻辑。

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