专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20110210444A1 3D Semiconductor Package Using An Interposer 有权
标题翻译：使用内插器的3D半导体封装
公开(公告)号：US20110210444A1
公开(公告)日：2011-09-01
申请号：US12813212
申请日：2010-06-10
申请人： Shin-Puu Jeng , Kim Hong Chen , Shang-Yun Hou , Chao-Wen Shih , Cheng-Chieh Hsieh , Chen-Hua Yu
发明人： Shin-Puu Jeng , Kim Hong Chen , Shang-Yun Hou , Chao-Wen Shih , Cheng-Chieh Hsieh , Chen-Hua Yu
IPC分类号： H01L23/538 , H01L21/60 , H01L23/488
CPC分类号： H01L25/50 , H01L23/13 , H01L23/3677 , H01L23/42 , H01L23/49827 , H01L23/49833 , H01L24/16 , H01L24/97 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/12042 , H01L2924/14 , H01L2924/1532 , H01L2924/00012 , H01L2224/81 , H01L2224/83 , H01L2924/00
摘要： A 3D semiconductor package using an interposer is provided. In an embodiment, an interposer is provided having a first die electrically coupled to a first side of the interposer and a second die electrically coupled to a second side of the interposer. The interposer is electrically coupled to an underlying substrate, such as a packaging substrate, a high-density interconnect, a printed circuit board, or the like. The substrate has a cavity such that the second die is positioned within the cavity. The use of a cavity may allow smaller conductive bumps to be used, thereby allowing a higher number of conductive bumps to be used. A heat sink may be placed within the cavity to aid in the dissipation of the heat from the second die.
摘要翻译：提供了使用插入器的3D半导体封装。在一个实施例中，提供了具有电耦合到插入器的第一侧的第一管芯的插入器和电耦合到插入件的第二侧的第二管芯。插入器电耦合到诸如封装衬底，高密度互连，印刷电路板等的下面的衬底。衬底具有腔，使得第二管芯位于腔内。使用空腔可以允许使用更小的导电凸块，从而允许使用更多数量的导电凸块。散热器可以放置在空腔内以帮助从第二模具散热。

2. 发明授权

US08519537B2 3D semiconductor package interposer with die cavity 有权
标题翻译：具有模腔的3D半导体封装插入器
公开(公告)号：US08519537B2
公开(公告)日：2013-08-27
申请号：US12813212
申请日：2010-06-10
申请人： Shin-Puu Jeng , Kim Hong Chen , Shang-Yun Hou , Chao-Wen Shih , Cheng-Chieh Hsieh , Chen-Hua Yu
发明人： Shin-Puu Jeng , Kim Hong Chen , Shang-Yun Hou , Chao-Wen Shih , Cheng-Chieh Hsieh , Chen-Hua Yu
IPC分类号： H01L23/13 , H01L23/538 , H01L23/488
CPC分类号： H01L25/50 , H01L23/13 , H01L23/3677 , H01L23/42 , H01L23/49827 , H01L23/49833 , H01L24/16 , H01L24/97 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/12042 , H01L2924/14 , H01L2924/1532 , H01L2924/00012 , H01L2224/81 , H01L2224/83 , H01L2924/00
摘要： A 3D semiconductor package using an interposer is provided. In an embodiment, an interposer is provided having a first die electrically coupled to a first side of the interposer and a second die electrically coupled to a second side of the interposer. The interposer is electrically coupled to an underlying substrate, such as a packaging substrate, a high-density interconnect, a printed circuit board, or the like. The substrate has a cavity such that the second die is positioned within the cavity. The use of a cavity may allow smaller conductive bumps to be used, thereby allowing a higher number of conductive bumps to be used. A heat sink may be placed within the cavity to aid in the dissipation of the heat from the second die.
摘要翻译：提供了使用插入器的3D半导体封装。在一个实施例中，提供了具有电耦合到插入器的第一侧的第一管芯的插入器和电耦合到插入件的第二侧的第二管芯。插入器电耦合到诸如封装衬底，高密度互连，印刷电路板等的下面的衬底。衬底具有腔，使得第二管芯位于腔内。使用空腔可以允许使用更小的导电凸块，从而允许使用更多数量的导电凸块。散热器可以放置在空腔内以帮助从第二模具散热。

3. 发明授权

US08283781B2 Semiconductor device having pad structure with stress buffer layer 有权
标题翻译：具有应力缓冲层的衬垫结构的半导体器件
公开(公告)号：US08283781B2
公开(公告)日：2012-10-09
申请号：US12879512
申请日：2010-09-10
申请人： Wei-Cheng Wu , Shang-Yun Hou , Shin-Puu Jeng , Tzuan-Horng Liu , Tzu-Wei Chiu , Chao-Wen Shih
发明人： Wei-Cheng Wu , Shang-Yun Hou , Shin-Puu Jeng , Tzuan-Horng Liu , Tzu-Wei Chiu , Chao-Wen Shih
IPC分类号： H01L29/40
CPC分类号： H01L24/11 , H01L23/3114 , H01L23/3157 , H01L23/525 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/02126 , H01L2224/0235 , H01L2224/0345 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05005 , H01L2224/05008 , H01L2224/05012 , H01L2224/05014 , H01L2224/05015 , H01L2224/05018 , H01L2224/05022 , H01L2224/05027 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05541 , H01L2224/05558 , H01L2224/05559 , H01L2224/05562 , H01L2224/05572 , H01L2224/05573 , H01L2224/05582 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/05687 , H01L2224/06131 , H01L2224/10126 , H01L2224/1132 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11849 , H01L2224/11912 , H01L2224/1308 , H01L2224/13083 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/94 , H01L2924/00014 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/35 , H01L2924/3512 , H01L2924/35121 , H01L2224/03 , H01L2224/11 , H01L2924/04941 , H01L2924/04953 , H01L2924/01028 , H01L2924/01022 , H01L2924/01083 , H01L2924/01051 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.
摘要翻译：半导体器件具有在金属焊盘和凸块下金属化（UBM）层之间具有环形应力缓冲层的焊盘结构。应力缓冲层由介电常数小于3.5的介质层，聚合物层或铝层形成。应力缓冲层是圆形环，方形环，八角形环或任何其它几何环。

4. 发明申请

US20120061823A1 SEMICONDUCTOR DEVICE HAVING PAD STRUCTURE WITH STRESS BUFFER LAYER 有权
标题翻译：具有应力缓冲层的平面结构的半导体器件
公开(公告)号：US20120061823A1
公开(公告)日：2012-03-15
申请号：US12879512
申请日：2010-09-10
申请人： Wei-Cheng WU , Shang-Yun HOU , Shin-Puu JENG , Tzuan-Horng LIU , Tzu-Wei CHIU , Chao-Wen Shih
发明人： Wei-Cheng WU , Shang-Yun HOU , Shin-Puu JENG , Tzuan-Horng LIU , Tzu-Wei CHIU , Chao-Wen Shih
IPC分类号： H01L23/498 , H01L23/485 , H01L23/482 , H01L21/768
CPC分类号： H01L24/11 , H01L23/3114 , H01L23/3157 , H01L23/525 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/02126 , H01L2224/0235 , H01L2224/0345 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05005 , H01L2224/05008 , H01L2224/05012 , H01L2224/05014 , H01L2224/05015 , H01L2224/05018 , H01L2224/05022 , H01L2224/05027 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05541 , H01L2224/05558 , H01L2224/05559 , H01L2224/05562 , H01L2224/05572 , H01L2224/05573 , H01L2224/05582 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/05687 , H01L2224/06131 , H01L2224/10126 , H01L2224/1132 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11849 , H01L2224/11912 , H01L2224/1308 , H01L2224/13083 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/94 , H01L2924/00014 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/35 , H01L2924/3512 , H01L2924/35121 , H01L2224/03 , H01L2224/11 , H01L2924/04941 , H01L2924/04953 , H01L2924/01028 , H01L2924/01022 , H01L2924/01083 , H01L2924/01051 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.
摘要翻译：半导体器件具有在金属焊盘和凸块下金属化（UBM）层之间具有环形应力缓冲层的焊盘结构。应力缓冲层由介电常数小于3.5的介质层，聚合物层或铝层形成。应力缓冲层是圆形环，方形环，八角形环或任何其它几何环。

5. 发明申请

US20120018877A1 Package-on-Package Structures with Reduced Bump Bridging 有权
标题翻译：封装封装结构，具有减小的凸块桥接
公开(公告)号：US20120018877A1
公开(公告)日：2012-01-26
申请号：US12843549
申请日：2010-07-26
申请人： Chung-Ying Yang , Chao-Wen Shih , Hao-Yi Tsai , Hsien-Wei Chen , Mirng-Ji Lii , Tzuan-Horng Liu
发明人： Chung-Ying Yang , Chao-Wen Shih , Hao-Yi Tsai , Hsien-Wei Chen , Mirng-Ji Lii , Tzuan-Horng Liu
IPC分类号： H01L23/538 , H01L23/488
CPC分类号： H01L23/5385 , H01L23/3121 , H01L23/5384 , H01L24/16 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/105 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/32225 , H01L2224/451 , H01L2224/48227 , H01L2224/73204 , H01L2225/0651 , H01L2225/06517 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A device includes a package substrate including a first non-reflowable metal bump extending over a top surface of the package substrate; a die over and bonded to the package substrate; and a package component over the die and bonded to the package substrate. The package component includes a second non-reflowable metal bump extending below a bottom surface of the package component. The package component is selected from the group consisting essentially of a device die, an additional package substrate, and combinations thereof. A solder bump bonds the first non-reflowable metal bump to the second non-reflowable metal bump.
摘要翻译：一种器件包括封装衬底，其包括在封装衬底的顶表面上延伸的第一不可回流金属凸块; 并且结合到封装基板上; 以及在所述管芯上并且结合到所述封装衬底的封装部件。包装部件包括在包装部件的底部表面下方延伸的第二不可回流金属凸块。封装部件选自基本上由器件管芯，附加封装衬底及其组合组成的组。焊料凸块将第一不可回流金属凸块接合到第二不可回流金属凸块。

6. 发明申请

US20090146317A1 PACKAGE SUBSTRATE HAVING ELECTRICALLY CONNECTING STRUCTURE 有权
标题翻译：具有电连接结构的封装基板
公开(公告)号：US20090146317A1
公开(公告)日：2009-06-11
申请号：US12265305
申请日：2008-11-05
申请人： Chao-Wen Shih
发明人： Chao-Wen Shih
IPC分类号： H01L23/52
CPC分类号： H01L23/49811 , H01L24/11 , H01L2224/0361 , H01L2224/03912
摘要： A package substrate having an electrically connecting structure are provided. The package substrate include: a package substrate substance with at least a surface having a plurality of electrically connecting pads formed thereon, allowing an insulating protective layer to be formed on the surface of the package substrate substance and the electrically connecting pads and formed with a plurality of openings corresponding in position to the electrically connecting pads so as to expose a portion of the electrically connecting pads, respectively; and a metal layer provided on an exposed portion of the electrically connecting pads, walls of the openings of the insulating protective layer, and a circular portion of the insulating protective layer encircling each of the openings thereof, and provided with a slope corresponding in position to a bottom rim of each of the openings. Accordingly, solder bleeding and short circuits are prevented.
摘要翻译：提供具有电连接结构的封装基板。封装基板包括：至少具有形成在其上的多个电连接焊盘的表面的封装基板物质，允许在封装基板物质和电连接焊盘的表面上形成绝缘保护层并形成多个的开口对应于电连接焊盘的位置，以分别暴露电连接焊盘的一部分; 以及金属层，其设置在所述电连接焊盘的露出部分，所述绝缘保护层的所述开口的壁以及所述绝缘保护层的围绕其每个所述开口的圆形部分，并且设置有对应于每个开口的底边缘。因此，防止了焊料渗出和短路。

7. 发明授权

US07419897B2 Method of fabricating circuit board having different electrical connection structures 有权
标题翻译：制造具有不同电连接结构的电路板的方法
公开(公告)号：US07419897B2
公开(公告)日：2008-09-02
申请号：US11759210
申请日：2007-06-06
申请人： Chao-Wen Shih
发明人： Chao-Wen Shih
IPC分类号： H01L21/44
CPC分类号： H01L21/4853 , H01L21/4846 , H01L23/49838 , H01L2224/0401 , H01L2224/05018 , H01L2224/05027 , H01L2224/05559 , H01L2224/05572 , H01L2224/13006 , H01L2224/13562 , H01L2924/0002 , H05K1/111 , H05K3/243 , H05K3/28 , H05K2201/0367 , H05K2201/0391 , H05K2201/09381 , H05K2201/09436 , H05K2201/10636 , Y02P70/611 , H01L2224/05552
摘要： A method of fabricating an electrical connecting structure of a circuit board is disclosed. The method includes: providing a circuit board having a plurality of first and a plurality of second conductive pads; forming on the circuit board a solder mask having a plurality of openings to thereby expose the first and the second conductive pads; forming an metal adhesive layer on the first and the second conductive pads; forming a conductive layer on the circuit board and the metal adhesive layer; forming on the conductive layer a resistive layer, wherein a plurality of openings are formed in the resistive layer to expose the conductive layer on the second conductive pads; forming a metal post by electroplating through the conductive layer on the second conductive pads; removing the resistive layer and the conductive layer covered underneath; and forming a soldering layer on the metal post.
摘要翻译：公开了一种制造电路板的电连接结构的方法。该方法包括：提供具有多个第一和多个第二导电焊盘的电路板; 在所述电路板上形成具有多个开口的焊料掩模，从而暴露所述第一和第二导电焊盘; 在第一和第二导电焊盘上形成金属粘合剂层; 在电路板和金属粘合剂层上形成导电层; 在所述导电层上形成电阻层，其中在所述电阻层中形成多个开口以暴露所述第二导电焊盘上的导电层; 通过电镀穿过第二导电焊盘上的导电层形成金属柱; 去除覆盖在下面的电阻层和导电层; 并在金属柱上形成焊接层。

8. 发明授权

US07365272B2 Circuit board with identifiable information and method for fabricating the same 有权
公开(公告)号：US07365272B2
公开(公告)日：2008-04-29
申请号：US10921832
申请日：2004-08-20
申请人： Shih-Ping Hsu , Shang-Wei Chen , Suo-Hsia Tang , Chao-Wen Shih
发明人： Shih-Ping Hsu , Shang-Wei Chen , Suo-Hsia Tang , Chao-Wen Shih
IPC分类号： H05K1/00
CPC分类号： H05K1/0266 , H05K1/0269 , H05K3/107 , H05K3/4644 , H05K2201/09781 , H05K2201/09927 , H05K2201/09936
摘要： A circuit board with identifiable information and a method for fabricating the same are proposed. At least one insulating layer within the circuit board has a non-circuit area free of a circuit layout. A plurality of openings are formed in the non-circuit area of the insulating layer. A patterned circuit layer is formed on the insulating layer. Metal identifiable information is disposed in the openings of the non-circuit area. By this arrangement, a product status of the circuit board can be traced and identified via the metal patterned information.

9. 发明申请

US20080054443A1 Carrier board structure with semiconductor chip embedded therein 审中-公开
标题翻译：载体板结构，其中嵌入有半导体芯片
公开(公告)号：US20080054443A1
公开(公告)日：2008-03-06
申请号：US11508708
申请日：2006-08-23
申请人： Chao-Wen Shih
发明人： Chao-Wen Shih
IPC分类号： H01L23/04
CPC分类号： H01L23/5389 , H01L23/49827 , H01L24/19 , H01L24/24 , H01L24/82 , H01L2224/24227 , H01L2924/01027 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/15153 , H01L2924/15165 , H01L2924/18162 , H01L2924/351 , H05K1/185 , H05K3/4602 , H05K2201/0187 , H05K2201/09827 , H05K2201/10674 , H01L2924/00
摘要： A carrier board structure with semiconductor chip embedded therein is proposed. The carrier board structure includes a carrier board having a first surface and a second surface opposed to the first surface, wherein the carrier board including at least one cavity having a chamfer. A semiconductor chip can be easily disposed in the cavity by the chamfer, and an adhesion material can be evenly filled in the cavity by the chamfer, so as to avoid generating air bubbles, voids and reduce stress.
摘要翻译：提出了一种其中嵌有半导体芯片的载板结构。载体板结构包括具有与第一表面相对的第一表面和第二表面的载体板，其中载体板包括具有倒角的至少一个空腔。半导体芯片可以通过倒角容易地设置在空腔中，并且可以通过倒角将粘合材料均匀地填充在空腔中，以避免产生气泡，空隙并减少应力。

10. 发明申请

US20060051952A1 Method for fabricating conductive bump of circuit board 有权
标题翻译：电路板导电凸块的制造方法
公开(公告)号：US20060051952A1
公开(公告)日：2006-03-09
申请号：US11079389
申请日：2005-03-15
申请人： Shih-Ping Hsu , Sao-Hsia Tang , Ying-Tung Wang , Wen-Hung Hu , Chao-Wen Shih , Meng-Da Chou
发明人： Shih-Ping Hsu , Sao-Hsia Tang , Ying-Tung Wang , Wen-Hung Hu , Chao-Wen Shih , Meng-Da Chou
IPC分类号： H01L21/44
CPC分类号： H05K3/3473 , H01L21/4853 , H01L23/49816 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H05K3/242 , H05K3/4602 , H05K2201/0352 , H05K2201/09436 , H05K2201/096 , H05K2203/043 , H05K2203/054 , H05K2203/0574 , H05K2203/1476 , H05K2203/1572 , H05K2203/1581 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A method for fabricating conductive bumps of a circuit board is proposed. First of all, a circuit board having a first surface and a corresponding second surface is provided. A circuit structure having a plurality of conductive pads is formed on each of the first surface and the second surface, and conductive structures are formed in the circuit board for electrically connecting the circuit structures. Also, an insulating layer having a plurality of openings penetrating therethrough is formed on the circuit board for exposing the conductive pad. Then, a conductive layer is formed on a surface of the insulating layer having the opening formed on the first surface of the circuit board. An electroplating process is performed via the conductive layer and the conductive structure, such that a conductive bump is formed on the conductive pad located on the second surface of the circuit board. Subsequently, a resist layer is formed on the second surface of the circuit board to cover the conductive bump, and another resist layer having openings penetrating therethrough is formed on the first surface of the circuit board to expose the conductive pad. Finally, a conductive bump is formed on the conductive pad located on the first surface of the circuit board by an electroplating process. By such arrangement, the conductive bumps are successively formed on the first surface and the second surface of the circuit board.
摘要翻译：提出了一种用于制造电路板的导电凸块的方法。首先，提供具有第一表面和相应的第二表面的电路板。在所述第一表面和所述第二表面中的每一个上形成具有多个导电焊盘的电路结构，并且在所述电路板中形成导电结构以电连接所述电路结构。此外，在电路板上形成具有贯穿其中的多个开口的绝缘层，用于暴露导电焊盘。然后，在具有形成在电路板的第一表面上的开口的绝缘层的表面上形成导电层。通过导电层和导电结构进行电镀处理，使得在位于电路板的第二表面上的导电焊盘上形成导电凸块。随后，在电路板的第二表面上形成抗蚀剂层以覆盖导电凸块，并且在电路板的第一表面上形成具有贯穿其中的开口的另一个抗蚀剂层，以露出导电焊盘。最后，通过电镀工艺在位于电路板的第一表面上的导电焊盘上形成导电凸块。通过这种布置，导电凸块依次形成在电路板的第一表面和第二表面上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式