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1. 发明授权

US07153755B2 Process to improve programming of memory cells 有权
标题翻译：改善存储单元编程的过程
公开(公告)号：US07153755B2
公开(公告)日：2006-12-26
申请号：US11044813
申请日：2005-01-26
申请人： Shih-Chang Liu , Wen-Ting Chu , Chien-Ming Ku , Chi-Hsin Lo , Chia-Shiung Tsai , Chia-Ta Hsieh
发明人： Shih-Chang Liu , Wen-Ting Chu , Chien-Ming Ku , Chi-Hsin Lo , Chia-Shiung Tsai , Chia-Ta Hsieh
IPC分类号： H01L21/762
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/10894 , H01L27/11
摘要： A method is provided for fabrication of a semiconductor substrate having regions isolated from each other by shallow trench isolation (STI) structures protruding above a surface of the substrate by a step height. The method includes the steps of forming a bottom antireflective coating (BARC) layer overlying the surface of a semiconductor substrate and the surface of STI structures; etching back a portion of the BARC layer overlying at least one of the STI structures, and partially etching back the at least one of the STI structures, to reduce the step height by which the STI structure protrudes above the surface of the substrate; and removing a remaining portion of the BARC layer between adjacent STI structures. The method may be used to fabricate semiconductor devices including memory cells that have improved reliability.
摘要翻译：提供了一种用于制造半导体衬底的方法，该半导体衬底具有通过在衬底的表面上突出台阶高度的浅沟槽隔离（STI）结构彼此隔离的区域。该方法包括以下步骤：形成覆盖半导体衬底的表面和STI结构表面的底部抗反射涂层（BARC）层; 蚀刻覆盖所述STI结构中的至少一个的所述BARC层的一部分，并且部分地蚀刻所述STI结构中的所述至少一个，以降低所述STI结构在所述衬底的表面上方突出的台阶高度; 以及去除相邻STI结构之间的BARC层的剩余部分。该方法可用于制造包括具有改进的可靠性的存储器单元的半导体器件。

2. 发明申请

US20060163686A1 Novel process to improve programming of memory cells 有权
标题翻译：改进存储单元编程的新过程
公开(公告)号：US20060163686A1
公开(公告)日：2006-07-27
申请号：US11044813
申请日：2005-01-26
申请人： Shih-Chang Liu , Wen-Ting Chu , Chien-Ming Ku , Chi-Hsin Lo , Chia-Shiung Tsai , Chia-Ta Hsieh
发明人： Shih-Chang Liu , Wen-Ting Chu , Chien-Ming Ku , Chi-Hsin Lo , Chia-Shiung Tsai , Chia-Ta Hsieh
IPC分类号： H01L21/76 , H01L29/00
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/10894 , H01L27/11
摘要： A method is provided for fabrication of a semiconductor substrate having regions isolated from each other by shallow trench isolation (STI) structures protruding above a surface of the substrate by a step height. The method includes the steps of forming a bottom antireflective coating (BARC) layer overlying the surface of a semiconductor substrate and the surface of STI structures; etching back a portion of the BARC layer overlying at least one of the STI structures, and partially etching back the at least one of the STI structures, to reduce the step height by which the STI structure protrudes above the surface of the substrate; and removing a remaining portion of the BARC layer between adjacent STI structures. The method may be used to fabricate semiconductor devices including memory cells that have improved reliability.
摘要翻译：提供了一种用于制造半导体衬底的方法，该半导体衬底具有通过在衬底的表面上突出台阶高度的浅沟槽隔离（STI）结构彼此隔离的区域。该方法包括以下步骤：形成覆盖在半导体衬底的表面上的底部抗反射涂层（BARC）层和STI结构的表面; 蚀刻覆盖所述STI结构中的至少一个的所述BARC层的一部分，并且部分地蚀刻所述STI结构中的所述至少一个，以降低所述STI结构在所述衬底的表面上方突出的台阶高度; 以及去除相邻STI结构之间的BARC层的剩余部分。该方法可用于制造包括具有改进的可靠性的存储器单元的半导体器件。

3. 发明授权

US07297598B2 Process for erase improvement in a non-volatile memory device 有权
标题翻译：在非易失性存储器件中擦除改进的过程
公开(公告)号：US07297598B2
公开(公告)日：2007-11-20
申请号：US11045850
申请日：2005-01-28
申请人： Shih-Chang Liu , Chi-Hsin Lo , Shih-Chi Fu , Chia-Ta Hsieh , Wen-Ting Chu , Chia-Shiung Tsai
发明人： Shih-Chang Liu , Chi-Hsin Lo , Shih-Chi Fu , Chia-Ta Hsieh , Wen-Ting Chu , Chia-Shiung Tsai
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115
摘要： A method of making embedded non-volatile memory devices includes forming a first mask layer overlying a polycrystalline silicon layer in a cell region and a peripheral region on a semiconductor substrate wherein the first mask layer has a plurality of openings in the cell region. Portions of the polycrystalline silicon layer exposed in the plurality of openings can be oxidized to form a plurality of poly-oxide regions, and the first mask layer can then be removed. The polycrystalline silicon layer not covered by the plurality of poly-oxide regions can be etched to form a plurality of floating gates, wherein etching the polycrystalline silicon layer is accompanied by a sputtering. A dielectric layer can then be formed, as well as a second mask layer in both the cell region and the peripheral region. The second mask layer in the cell region is partially etched back after a photoresist layer is formed over the second mask layer in the peripheral region. The dielectric layer is partially etched to form multiple thicknesses of the dielectric layer. The second mask layer is removed and a plurality of control gates are formed partially overlying the plurality of floating gates in the cell region.
摘要翻译：一种制造嵌入式非易失性存储器件的方法包括形成覆盖单元区域中的多晶硅层的第一掩模层和半导体衬底上的外围区域，其中第一掩模层在单元区域中具有多个开口。在多个开口中暴露的多晶硅层的一部分可以被氧化以形成多个多晶氧化物区域，然后可以去除第一掩模层。可以蚀刻不被多个多晶氧化物区域覆盖的多晶硅层以形成多个浮栅，其中蚀刻多晶硅层伴随着溅射。然后可以形成电介质层，以及在电池区域和周边区域中形成第二掩模层。在周边区域中的第二掩模层上形成光致抗蚀剂层之后，单元区域中的第二掩模层被部分地回蚀。电介质层被部分蚀刻以形成介电层的多个厚度。去除第二掩模层，并且多个控制栅极部分地覆盖在单元区域中的多个浮动栅极上。

4. 发明申请

US20060170029A1 Novel process for erase improvement in a non-volatile memory device 有权
标题翻译：用于擦除非易失性存储器件中的擦除的新方法
公开(公告)号：US20060170029A1
公开(公告)日：2006-08-03
申请号：US11045850
申请日：2005-01-28
申请人： Shih-Chang Liu , Chi-Hsin Lo , Shih-Chi Fu , Chia-Ta Hsieh , Wen-Ting Chu , Chia-Shiung Tsai
发明人： Shih-Chang Liu , Chi-Hsin Lo , Shih-Chi Fu , Chia-Ta Hsieh , Wen-Ting Chu , Chia-Shiung Tsai
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115
摘要： A method of making embedded non-volatile memory devices includes forming a first mask layer overlying a polycrystalline silicon layer in a cell region and a peripheral region on a semiconductor substrate wherein the first mask layer has a plurality of openings in the cell region. Portions of the polycrystalline silicon layer exposed in the plurality of openings can be oxidized to form a plurality of poly-oxide regions, and the first mask layer can then be removed. The polycrystalline silicon layer not covered by the plurality of poly-oxide regions can be etched to form a plurality of floating gates, wherein etching the polycrystalline silicon layer is accompanied by a sputtering. A dielectric layer can then be formed, as well as a second mask layer in both the cell region and the peripheral region. The second mask layer in the cell region is partially etched back after a photoresist layer is formed over the second mask layer in the peripheral region. The dielectric layer is partially etched to form multiple thicknesses of the dielectric layer. The second mask layer is removed and a plurality of control gates are formed partially overlying the plurality of floating gates in the cell region.
摘要翻译：一种制造嵌入式非易失性存储器件的方法包括形成覆盖单元区域中的多晶硅层的第一掩模层和半导体衬底上的外围区域，其中第一掩模层在单元区域中具有多个开口。在多个开口中暴露的多晶硅层的一部分可以被氧化以形成多个多晶氧化物区域，然后可以去除第一掩模层。可以蚀刻不被多个多晶氧化物区域覆盖的多晶硅层以形成多个浮栅，其中蚀刻多晶硅层伴随着溅射。然后可以形成电介质层，以及在电池区域和周边区域中形成第二掩模层。在周边区域中的第二掩模层上形成光致抗蚀剂层之后，单元区域中的第二掩模层被部分地回蚀。电介质层被部分蚀刻以形成介电层的多个厚度。去除第二掩模层，并且多个控制栅极部分地覆盖在单元区域中的多个浮动栅极上。

5. 发明申请

US20080149985A1 METHOD FOR FABRICATING FLOATING GATES STRUCTURES WITH REDUCED AND MORE UNIFORM FORWARD TUNNELING VOLTAGES 有权
标题翻译：具有减少和更均匀的前向隧道电压的浮动门结构的制造方法
公开(公告)号：US20080149985A1
公开(公告)日：2008-06-26
申请号：US11614677
申请日：2006-12-21
申请人： Shih-Chang Liu , Wen-Ting Chu , Chi-Hsin Lo , Chia-Shiung Tsai
发明人： Shih-Chang Liu , Wen-Ting Chu , Chi-Hsin Lo , Chia-Shiung Tsai
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , Y10S438/981
摘要： An improved method for fabricating floating gate structures of flash memory cells having reduced and more uniform forward tunneling voltages. The method may include the steps of: forming at least two floating gates over a substrate; forming a mask over each of the floating gates, each of the masks having a portion, adjacent to a tip of a respective one of the floating gates, of a given thickness, wherein the given thicknesses of the mask portions are different from one another; and etching the masks to reduce the different given thicknesses of the mask portions to a reduced thickness wherein the reduced thickness portions of the mask are of a uniform thickness.
摘要翻译：一种用于制造具有减小且更均匀的前向隧道电压的闪存单元的浮动栅极结构的改进方法。该方法可以包括以下步骤：在衬底上形成至少两个浮动栅极; 在每个浮动栅极上形成掩模，每个掩模具有与给定厚度的相应一个浮动栅极的尖端相邻的部分，其中掩模部分的给定厚度彼此不同; 并且蚀刻掩模以将掩模部分的不同给定厚度减小到减小的厚度，其中掩模的厚度减小部分具有均匀的厚度。

6. 发明授权

US07785966B2 Method for fabricating floating gates structures with reduced and more uniform forward tunneling voltages 有权
标题翻译：用于制造具有减小且更均匀的前向隧穿电压的浮动栅极结构的方法
公开(公告)号：US07785966B2
公开(公告)日：2010-08-31
申请号：US11614677
申请日：2006-12-21
申请人： Shih-Chang Liu , Wen-Ting Chu , Chi-Hsin Lo , Chia-Shiung Tsai
发明人： Shih-Chang Liu , Wen-Ting Chu , Chi-Hsin Lo , Chia-Shiung Tsai
IPC分类号： H01L21/8247
CPC分类号： H01L21/28273 , Y10S438/981
摘要： An improved method for fabricating floating gate structures of flash memory cells having reduced and more uniform forward tunneling voltages. The method may include the steps of: forming at least two floating gates over a substrate; forming a mask over each of the floating gates, each of the masks having a portion, adjacent to a tip of a respective one of the floating gates, of a given thickness, wherein the given thicknesses of the mask portions are different from one another; and etching the masks to reduce the different given thicknesses of the mask portions to a reduced thickness wherein the reduced thickness portions of the mask are of a uniform thickness.
摘要翻译：一种用于制造具有减小且更均匀的前向隧道电压的闪存单元的浮动栅极结构的改进方法。该方法可以包括以下步骤：在衬底上形成至少两个浮动栅极; 在每个浮动栅极上形成掩模，每个掩模具有与给定厚度的相应一个浮动栅极的尖端相邻的部分，其中掩模部分的给定厚度彼此不同; 并且蚀刻掩模以将掩模部分的不同给定厚度减小到减小的厚度，其中掩模的厚度减小部分具有均匀的厚度。

7. 发明申请

US20080121975A1 Split-gate memory cells and fabrication methods thereof 有权
标题翻译：分离栅存储单元及其制造方法
公开(公告)号：US20080121975A1
公开(公告)日：2008-05-29
申请号：US11592290
申请日：2006-11-03
申请人： Chang-Jen Hsieh , Hung-Cheng Sung , Wen-Ting Chu , Chen-Ming Huang , Ya-Chen Kao , Shih-Chang Liu , Chi-Hsin Lo , Chung-Yi Yu , Chia-Shiung Tsai
发明人： Chang-Jen Hsieh , Hung-Cheng Sung , Wen-Ting Chu , Chen-Ming Huang , Ya-Chen Kao , Shih-Chang Liu , Chi-Hsin Lo , Chung-Yi Yu , Chia-Shiung Tsai
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions. A pair of control gates are self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates are disposed on the outer sidewalls of the pair of control gates along the second direction.
摘要翻译：分离栅存储单元及其制造方法。分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，在限定具有一对漏极和源极区域的有源区域的两个相邻隔离区域之间。一对浮置栅极设置在有源区上并与隔离区自对准，其中浮置栅极的顶层等于隔离区的顶层。一对控制栅极与浮动栅极自对准并沿着第二方向设置在浮动栅极上。源极线沿第二方向设置在该对控制栅极之间。一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

8. 发明申请

US20080105917A1 Split-gate memory cells and fabrication methods thereof 失效
标题翻译：分离栅存储单元及其制造方法
公开(公告)号：US20080105917A1
公开(公告)日：2008-05-08
申请号：US11785382
申请日：2007-04-17
申请人： Chang-Jen Hsieh , Hung-Cheng Sung , Wen-Ting Chu , Chen-Ming Huang , Ya-Chen Kao , Shih-Chang Liu , Chi-Hsin Lo , Chung-Yi Yu , Chia-Shiung Tsai
发明人： Chang-Jen Hsieh , Hung-Cheng Sung , Wen-Ting Chu , Chen-Ming Huang , Ya-Chen Kao , Shih-Chang Liu , Chi-Hsin Lo , Chung-Yi Yu , Chia-Shiung Tsai
IPC分类号： H01L29/788 , H01L27/115
CPC分类号： H01L27/115 , H01L27/11521
摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A top level of the active regions is lower than a top level of the isolation regions. A pair of floating gates is disposed on the active regions and aligned with the isolation regions, wherein a passivation layer is disposed on the floating gate to prevent thinning from CMP. A pair of control gates is self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates is disposed on the outer sidewalls of the pair of control gates along the second direction.
摘要翻译：分离栅存储单元及其制造方法。分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，两个相邻的隔离区域限定具有一对漏极和源极区域的有源区域。活动区域的顶层低于隔离区域的顶层。一对浮置栅极设置在有源区上并与隔离区对准，其中钝化层设置在浮栅上以防止CMP变薄。一对控制栅极与浮动栅极自对准，并沿第二方向设置在浮动栅极上。源极线沿第二方向设置在该对控制栅极之间。一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

9. 发明授权

US07667261B2 Split-gate memory cells and fabrication methods thereof 失效
标题翻译：分离栅存储单元及其制造方法
公开(公告)号：US07667261B2
公开(公告)日：2010-02-23
申请号：US11785382
申请日：2007-04-17
申请人： Chang-Jen Hsieh , Hung-Cheng Sung , Wen-Ting Chu , Chen-Ming Huang , Ya-Chen Kao , Shih-Chang Liu , Chi-Hsin Lo , Chung-Yi Yu , Chia-Shiung Tsai
发明人： Chang-Jen Hsieh , Hung-Cheng Sung , Wen-Ting Chu , Chen-Ming Huang , Ya-Chen Kao , Shih-Chang Liu , Chi-Hsin Lo , Chung-Yi Yu , Chia-Shiung Tsai
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A top level of the active regions is lower than a top level of the isolation regions. A pair of floating gates is disposed on the active regions and aligned with the isolation regions, wherein a passivation layer is disposed on the floating gate to prevent thinning from CMP. A pair of control gates is self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates is disposed on the outer sidewalls of the pair of control gates along the second direction.
摘要翻译：分离栅存储单元及其制造方法。分离栅存储器单元包括沿着第一方向在半导体衬底上形成的多个隔离区域，在限定具有一对漏极和源极区域的有源区域的两个相邻隔离区域之间。活动区域的顶层低于隔离区域的顶层。一对浮置栅极设置在有源区上并与隔离区对准，其中钝化层设置在浮栅上以防止CMP变薄。一对控制栅极与浮动栅极自对准，并沿第二方向设置在浮动栅极上。源极线沿第二方向设置在该对控制栅极之间。一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

10. 发明授权

US07652318B2 Split-gate memory cells and fabrication methods thereof 有权
标题翻译：分离栅存储单元及其制造方法
公开(公告)号：US07652318B2
公开(公告)日：2010-01-26
申请号：US11592290
申请日：2006-11-03
申请人： Chang-Jen Hsieh , Hung-Cheng Sung , Wen-Ting Chu , Chen-Ming Huang , Ya-Chen Kao , Shih-Chang Liu , Chi-Hsin Lo , Chung-Yi Yu , Chia-Shiung Tsai
发明人： Chang-Jen Hsieh , Hung-Cheng Sung , Wen-Ting Chu , Chen-Ming Huang , Ya-Chen Kao , Shih-Chang Liu , Chi-Hsin Lo , Chung-Yi Yu , Chia-Shiung Tsai
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions. A pair of control gates are self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates are disposed on the outer sidewalls of the pair of control gates along the second direction.
摘要翻译：分离栅存储单元及其制造方法。分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，两个相邻的隔离区域限定具有一对漏极和源极区域的有源区域。一对浮置栅极设置在有源区上并与隔离区自对准，其中浮置栅极的顶层等于隔离区的顶层。一对控制栅极与浮动栅极自对准并沿着第二方向设置在浮动栅极上。源极线沿第二方向设置在该对控制栅极之间。一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

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