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1. 发明授权

US5189474A Agitating member for a developing apparatus 失效
标题翻译：成立开发设备的成员
公开(公告)号：US5189474A
公开(公告)日：1993-02-23
申请号：US686973
申请日：1991-04-18
申请人： Shigeyuki Miya , Takenori Shibata , Yoshihiro Komatsu , Hiromichi Miyoshi , Tadashi Hirata , Yoshio Taniguchi , Takuo Kobayashi
发明人： Shigeyuki Miya , Takenori Shibata , Yoshihiro Komatsu , Hiromichi Miyoshi , Tadashi Hirata , Yoshio Taniguchi , Takuo Kobayashi
IPC分类号： B01F7/00 , B01F15/00 , G03G15/08
CPC分类号： B01F7/00391 , G03G15/0822 , G03G15/0853 , G03G15/0877 , G03G15/0879 , G03G15/0889
摘要： A developing apparatus of the type including a developing roller disposed in a development box, a stirring roller parallel spaced apart from the developing roller, and a toner replenisher pipe disposed in the stirring roller, wherein the stirring roller has a substantially hollow cylindrical shape and includes a plurality of axial ribs extending parallel to a longitudinal axis of the stirring roller and disposed equidistantly from the longitudinal axis, and a plurality of helical blades integral with the axial ribs and skewed relative to the longitudinal axis of the stirring roller, said hollow cylindrical stirring roller being composed of at least two identical segments which are divided by a plane extending through said longitudinal axis of said stirring roller. The stirring roller is simple in construction and can be manufactured at a low cost. The developing apparatus further includes a separator for receiving an excess developer which is removed from the outside surface of the developing roller and direct it unto the stirring roller.

2. 发明授权

US09705341B2 Electric storage apparatus, electronic device, electric vehicle, and electric power system including a magnetic core 有权
公开(公告)号：US09705341B2
公开(公告)日：2017-07-11
申请号：US13592950
申请日：2012-08-23
申请人： Yoshihiro Komatsu , Hidekazu Kikuchi , Koji Umetsu
发明人： Yoshihiro Komatsu , Hidekazu Kikuchi , Koji Umetsu
IPC分类号： B60L1/00 , H02J7/00
CPC分类号： H02J7/0019 , B60L11/1866 , H01F38/30 , H01M2/024 , H01M10/625 , H02J7/0014 , H02J7/0021 , Y02T10/7055
摘要： A battery system includes a plurality of electronic storage modules serially connected together. Each electronic storage module includes a battery block group including a plurality of battery cells, and a different magnetic core connected to each battery block group. An electronic device, an electric vehicle and electric power system including the battery system are also provided.

3. 发明授权

US08802534B2 Method for forming SOI substrate and apparatus for forming the same 有权
标题翻译：用于形成SOI衬底的方法及其形成装置
公开(公告)号：US08802534B2
公开(公告)日：2014-08-12
申请号：US13488854
申请日：2012-06-05
申请人： Yoshihiro Komatsu , Tomoaki Moriwaka , Kojiro Takahashi
发明人： Yoshihiro Komatsu , Tomoaki Moriwaka , Kojiro Takahashi
IPC分类号： H01L21/331 , H01L21/8222 , H01L21/84 , H01L21/762
CPC分类号： H01L21/84 , H01L21/67092 , H01L21/7624 , H01L21/76254 , H01L27/1262 , H01L29/78654 , Y10S438/967
摘要： A bond substrate is attached with an incline toward the setting surface of a base substrate. Accordingly, an attachment starting portion can be limited. Further, the bond substrate is provided so that part of the bond substrate extends beyond a support base and the part is closest to the base substrate. Because of this, part of the bond substrate is separated from the support base with the use of an end portion of the support base as a fulcrum point because the support base is not provided below the contact portion, and attachment sequentially proceeds from a portion which gets close to the base substrate; thus, stable attachment can be performed without an air layer remaining at the interface between the bond substrate and the base substrate.
摘要翻译：接合基板朝向基底基板的设置表面倾斜地附接。因此，可以限制附件起始部分。此外，提供接合基板，使得接合基板的一部分延伸超过支撑基部，并且该部分最靠近基底。因此，由于支撑基底不设置在接触部的下方，所以借助于支撑基座的端部作为支点，将粘合基板的一部分与支撑基座分离，由此，依次从靠近基底; 因此，可以在粘合基板和基底基板之间的界面处没有空气层的情况下进行稳定的附着。

4. 发明授权

US08218706B2 Communication system, receiving apparatus, and receiving method 有权
标题翻译：通信系统，接收装置和接收方法
公开(公告)号：US08218706B2
公开(公告)日：2012-07-10
申请号：US12274706
申请日：2008-11-20
申请人： Hidekazu Kikuchi , Yoshihiro Komatsu , Masahiro Segami
发明人： Hidekazu Kikuchi , Yoshihiro Komatsu , Masahiro Segami
IPC分类号： H03D3/24
CPC分类号： H04L7/0008 , H03L7/07 , H03L7/0812 , H03L7/087 , H03L7/10 , H04L7/0037 , H04L7/0337
摘要： A communication system includes a transmission apparatus for transmitting a plurality of serial data signals that are synchronized in phase with one another and a clock signal that is synchronized in frequency with the serial data signals; and a receiving apparatus for receiving a plurality of serial data signals and the clock signal transmitted from the transmission apparatus. The receiving apparatus includes a phase synchronization circuit configured to roughly adjust the frequency in accordance with the received clock signal and then generate a reproduction clock that is synchronized in phase with one serial data signal among the plurality of serial data signals, and a phase shifter configured to shift the phase from the reproduction clock and lock the phase to another serial signal.
摘要翻译：通信系统包括：发送装置，用于发送与串行数据信号同步的多个串行数据信号和与频率同步的时钟信号; 以及接收装置，用于接收从发送装置发送的多个串行数据信号和时钟信号。接收装置包括：相位同步电路，被配置为根据所接收的时钟信号粗略地调整频率，然后产生与多个串行数据信号中的一个串行数据信号同相同步的再现时钟，并配置移相器将相位从再现时钟移位并将相位锁定到另一个串行信号。

5. 发明授权

US5200651A Collector dot and circuit 失效
标题翻译：收集点和电路
公开(公告)号：US5200651A
公开(公告)日：1993-04-06
申请号：US792616
申请日：1991-11-15
申请人： Yoshihiro Komatsu , Masato Kawata
发明人： Yoshihiro Komatsu , Masato Kawata
IPC分类号： H03M1/36 , H03K3/2885 , H03K19/086 , H03K19/20
CPC分类号： H03K3/2885 , H03K19/086
摘要： A multi-output collector dot AND circuit wherein a logical AND signal can be formed from a pair of adjacent circuits and another logical AND circuit can also be formed from a pair of circuits spaced from each other. The collector dot AND circuit comprises a plurality of output transistors which are cascade connected to an output electrode of one of a pair of transistors constituting a differential circuit so that an output or outputs different from an output which is used to obtain a logical AND signal together with an output of an adjacent differential circuit are obtained from the one transistor. A number of dummy transistors equal to the number of the output transistors are cascade connected to an output electrode of the other transistor. Further, a constant-current source is connected to the differential circuit such that an electric current which flows from each of the output transistors connected to the one transistor is made equal in magnitude to an electric current which flows from a transistor of the adjacent differential circuit.
摘要翻译：多输出收集点AND电路，其中可以由一对相邻电路形成逻辑“与”信号，另一逻辑与电路也可以由彼此间隔开的一对电路形成。集电极AND电路包括多个输出晶体管，其串联连接到构成差分电路的一对晶体管中的一个的输出电极，使得与用于一起获得逻辑“与”信号的输出不同的输出或输出从一个晶体管获得相邻差分电路的输出。等于输出晶体管数量的虚设晶体管的数量级联连接到另一晶体管的输出电极。此外，恒流源连接到差分电路，使得从连接到一个晶体管的每个输出晶体管流过的电流的大小与从相邻差分电路的晶体管流出的电流相等。

6. 发明申请

US20130059182A1 POWER STORAGE APPARATUS AND ELECTRIC VEHICLE 有权
标题翻译：蓄电装置和电动车
公开(公告)号：US20130059182A1
公开(公告)日：2013-03-07
申请号：US13598936
申请日：2012-08-30
申请人： Yoshihiro Komatsu , Hidekazu Kikuchi , Koji Umetsu , Naoyuki Sugeno , Morihiko Sato
发明人： Yoshihiro Komatsu , Hidekazu Kikuchi , Koji Umetsu , Naoyuki Sugeno , Morihiko Sato
IPC分类号： H01M10/48
CPC分类号： H01M10/482 , B60L1/00 , B60L11/1866 , B60L11/1879 , H01M2/1072 , H01M2/1077 , H01M10/4207 , H01M10/425 , H01M2010/4271 , H01M2010/4278 , H01M2220/20 , Y02T10/7005 , Y02T10/7061 , Y02T90/16
摘要： A power storage apparatus, electric device, electric vehicle, and power system are disclosed. In an example embodiment, a power storage apparatus includes a battery block comprising a plurality of battery cells and an isolating unit that enables wireless information transfer regarding battery information of the battery block.
摘要翻译：公开了蓄电装置，电气装置，电动车辆和动力系统。在一个示例性实施例中，一种蓄电装置包括：电池块，包括多个电池单元;以及隔离单元，其能够关于电池块的电池信息的无线信息传输。

7. 发明授权

US08367517B2 Method for manufacturing SOI substrate 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：US08367517B2
公开(公告)日：2013-02-05
申请号：US13011355
申请日：2011-01-21
申请人： Kazuya Hanaoka , Hideki Tsuya , Yoshihiro Komatsu
发明人： Kazuya Hanaoka , Hideki Tsuya , Yoshihiro Komatsu
IPC分类号： H01L21/30
CPC分类号： H01L21/76254 , H01L21/02032 , H01L21/3225 , H01L22/12 , H01L22/20
摘要： An insulating layer is formed over a surface of a semiconductor wafer to be the bond substrate and irradiation with accelerated ions is performed, so that an embrittlement region is formed inside the wafer. Next, this semiconductor wafer and a base substrate such as a glass substrate or a semiconductor wafer are attached to each other. Then, the semiconductor wafer is divided at the embrittlement region by heat treatment, whereby an SOI substrate is manufactured in which a semiconductor layer is provided over the base substrate with the insulating layer interposed therebetween. Before this SOI substrate is manufactured, heat treatment is performed on the semiconductor wafer at 1100° C. or higher under a non-oxidizing atmosphere such as an argon gas atmosphere or a mixed atmosphere of an oxygen gas and a nitrogen gas.
摘要翻译：在作为接合衬底的半导体晶片的表面上形成绝缘层，并且执行加速离子的照射，从而在晶片内形成脆化区域。接下来，将该半导体晶片和诸如玻璃基板或半导体晶片的基底基板彼此附接。然后，通过热处理将半导体晶片分割在脆化区域，由此制造SOI衬底，其中半导体层设置在基底衬底上，绝缘层置于其之间。在制造该SOI衬底之前，在诸如氩气气氛或氧气和氮气的混合气氛的非氧化性气氛下，在1100℃以上对半导体晶片进行热处理。

8. 发明授权

US5384569A Interpolation type flash analog-to-digital converter 失效
标题翻译：插补型闪存模数转换器
公开(公告)号：US5384569A
公开(公告)日：1995-01-24
申请号：US83970
申请日：1993-06-28
申请人： Yoshihiro Komatsu
发明人： Yoshihiro Komatsu
IPC分类号： H03M1/10 , H03M1/14 , H03M1/20 , H03M1/36
CPC分类号： H03M1/204 , H03M1/361
摘要： In an analog signal comparator circuit, first and second inversion output currents to the first and second reference values of input analog signals, a plurality of the first and second dividually inversion outputs divided the first and second non-inversion output currents, and the first and second dividually non inversion output currents are combined respectively and added, and the comparison output corresponding to the virtual reference value for dividing the first reference value, and the first reference value and the second reference value equally are outputted. Thus, the number of comparators can be decreased comparing with the necessary numbers of reference values, and by decreasing the number of elements the input capacities can be decreased and differential linearity errors can be reduced.
摘要翻译：在模拟信号比较器电路中，将第一和第二反相输出电流转换为输入模拟信号的第一和第二参考值，多个第一和第二单独反相输出分割第一和第二非反相输出电流，以及第一和第二非反相输出电流分别组合第二单独非反相输出电流，并且输出与用于划分第一参考值的虚拟参考值和第一参考值和第二参考值相等的比较输出。因此，与必要数量的参考值相比，可以减少比较器的数量，并且通过减少输入容量可以减少的元件的数量，并且可以减小差分线性误差。

9. 发明授权

US5223836A Subranging analog-to-digital converter with priority weighted correction for the m.s.b. group 失效
标题翻译：对m.s.b.进行优先权重校正的模数转换器。组
公开(公告)号：US5223836A
公开(公告)日：1993-06-29
申请号：US835359
申请日：1992-02-14
申请人： Yoshihiro Komatsu
发明人： Yoshihiro Komatsu
IPC分类号： H03M1/10 , H03M1/14 , H03M1/36
CPC分类号： H03M1/14 , H03M1/365
摘要： In an analog/digital conversion circuit, selection signals XA, XB and XC inputted from a lower order comparing circuit unit 5 are assigned priority by weighting the same, in a selection signal weighting circuit 11. When a plurality of the selection signals XA, XB and XC are raised up to an "H", in that, (XA, XB, XC), (XA, XB), (XA, XC) or (XB, XC), line signals SC, SB, and corresponding to weighted selection signals having a higher priority XBO, and XAO are outputted as a higher order conversion code data D1. Thereby a more reliable signal is outputted as the higher order conversion code even if an erroneous operation is caused in the lower order comparing circuit unit 5 and the accuracy of the analog/digital conversion circuit is further enhanced in comparison with the conventional ones.
摘要翻译：在模拟/数字转换电路中，通过对选择信号加权电路11进行加权，从低阶比较电路单元5输入的选择信号XA，XB和XC被赋予优先权。当多个选择信号XA，XB （XA，XB，XC），（XA，XB），（XA，XC）或（XB，XC）中的XC被提升为“H”，线信号SC，SB，具有较高优先级的选择信号XBO和XAO作为高阶转换代码数据D1输出。因此，即使在较低阶比较电路单元5中引起错误操作，也可以将更可靠的信号作为高阶转换代码输出，与常规转换代码相比，模/数转换电路的精度进一步提高。

10. 发明授权

US5170079A Collector dot and circuit with latched comparator 失效
标题翻译：集电极点和电路与锁存比较器
公开(公告)号：US5170079A
公开(公告)日：1992-12-08
申请号：US781593
申请日：1991-10-23
申请人： Yoshihiro Komatsu , Yuji Gendai
发明人： Yoshihiro Komatsu , Yuji Gendai
IPC分类号： H03K3/2885 , H03K19/086 , H03K19/20
CPC分类号： H03K19/086 , H03K3/2885
摘要： A logic circuit which can operate to form a logic AND signal of a predetermined voltage level in accordance with a potential difference between a plurality of input signals using a collector dot AND circuit and a latched comparator circuit without the necessity of provision of a NOT circuit or a level shifting circuit at a preceding stage to the logic circuit. The logic circuit comprises a collector dot AND circuit, a logic level outputting circuit and a plurality of emitter follower circuits. Output electrodes of those of the emitter followers which are connected to receive NOT signals of input signals developed from the collector dot AND circuit are coupled commonly to form a wired OR circuit, and an output of the wired OR circuit is supplied to a transistor of the logic level outputting circuit connected to receive a logic AND signal of the input signals developed from the collector dot AND circuit so as to form a NOT signal of the logic AND signal.
摘要翻译：逻辑电路，其可以根据使用收集点AND电路的多个输入信号和锁存比较器电路之间的电位差来形成预定电压电平的逻辑AND信号，而无需提供NOT电路或在逻辑电路的前级的电平移位电路。逻辑电路包括集电极AND电路，逻辑电平输出电路和多个射极跟随电路。连接到接收从收集点AND电路产生的输入信号的NOT信号的发射极跟随器的输出电极共同耦合以形成布线OR电路，并且布线OR电路的输出被提供给连接的逻辑电平输出电路接收从采集点AND电路产生的输入信号的逻辑“与”信号，以形成逻辑“与”信号的非信号。

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