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    • 1. 发明授权
    • Process for making semiconductor acceleration sensor having anti-etching
layer
    • 具有防腐蚀层的半导体加速度传感器的制造方法
    • US5395802A
    • 1995-03-07
    • US37335
    • 1993-03-26
    • Shigeyuki KiyotaHideo Muro
    • Shigeyuki KiyotaHideo Muro
    • B81B3/00G01P15/08G01P15/12H01L29/84H01L21/465
    • B81C1/00666B81C1/00595G01P15/0802G01P15/123B81B2201/0235B81B2203/0118B81B2203/0315B81C2201/014B81C2201/0177G01P2015/0828Y10S438/924
    • A semiconductor acceleration transducer is fabricated so that the semiconductor beam and the piezoelectric transducing element are accurately positioned relative to each other, and the impact resistance is improved. The fabrication process comprises a wafer preparing step for forming a buried layer between a substrate of a first conductivity type and an epitaxial layer of a second conductivity type, a doping step for forming a diffusion region of the first conductivity type in the epitaxial layer, and an etching step for removing unwanted portions of the substrate and the diffusion region from the bottom of the substrate to shape the beam supporting portion serving as a seismic mass. The buried layer is formed at such a position that the shape and position of the beam is determined by the buried layer. The buried layer may be a second conductivity type layer to determine the contour of the beam by stopping the etching process or may be a first conductivity type layer which is etched away to determine the contour of the beam with its diffusion contour.
    • 制造半导体加速度传感器,使得半导体束和压电换能元件相对于彼此精确地定位,并且提高了抗冲击性。 制造工艺包括用于在第一导电类型的衬底和第二导电类型的外延层之间形成掩埋层的晶片准备步骤,用于在外延层中形成第一导电类型的扩散区域的掺杂步骤,以及 蚀刻步骤,用于从衬底的底部除去衬底和扩散区的不需要的部分,以形成用作抗震质量的梁支撑部分。 掩埋层形成在这样的位置,即由掩埋层决定光束的形状和位置。 掩埋层可以是第二导电类型层,以通过停止蚀刻工艺来确定光束的轮廓,或者可以是蚀刻掉的第一导电类型层,以确定具有其扩散轮廓的光束的轮廓。
    • 2. 发明授权
    • Integrated circuit having surge protection circuit
    • 具有浪涌保护电路的集成电路
    • US6087877A
    • 2000-07-11
    • US110332
    • 1998-07-06
    • Tomohiko GondaShigeyuki Kiyota
    • Tomohiko GondaShigeyuki Kiyota
    • H01L27/04H01L21/822H02H7/20H02H9/04H03F1/52H03K5/08H03K17/082
    • H03K17/0822H03K5/08
    • A trailing edge of a control signal of a transistor controller for controlling an output transistor is detected by an edge detector of a clamp controlling circuit. A surge voltage from a back electromotive voltage induced in an inductance L1 is absorbed from the output transistor, only for a given period immediately after the solenoid is turned off, by turning a switching transistor into an on-state by a timer to force a clamping circuit into conduction. At a normal operation, since the clamping circuit is cut off from an output terminal, the clamping voltage can be set in a manner to reduce to a normal voltage in an IGN-line. Therefore, a peak power value of a power loss caused by the surge voltage at the output transistor can be reduced, whereby generation of heat at the output transistor can be reduced. Therefore, the chip size of the power IC can be reduced.
    • 用于控制输出晶体管的晶体管控制器的控制信号的后沿由钳位控制电路的边沿检测器检测。 在电感L1感应的反电动势电压的浪涌电压从输出晶体管吸收,仅在电磁阀断开之后的给定时间内,通过定时器将开关晶体管转换为导通状态,以强制钳位 电路导通。 在正常操作中,由于钳位电路与输出端子断开,因此可以将钳位电压设定为降低IGN线路中的正常电压。 因此,能够降低由输出晶体管的浪涌电压引起的功率损耗的峰值功率值,能够降低输出晶体管的发热量。 因此,可以降低功率IC的芯片尺寸。
    • 4. 发明授权
    • Configuration and test process for semiconductor overcurrent detecting
circuit
    • 半导体过电流检测电路的配置和测试过程
    • US5909112A
    • 1999-06-01
    • US42695
    • 1998-03-17
    • Shigeyuki KiyotaHironori Saito
    • Shigeyuki KiyotaHironori Saito
    • H02H3/08G01R19/165G01R31/28G05F1/573H02H3/087G05F1/56G05F3/16
    • G05F1/573
    • A MOSFET integrated circuit device has a main MOSFET, a mirror MOSFET, a current sensing resistor, a reference voltage source, a comparator for detecting an overcurrent condition by comparing a potential at the source of the mirror MOSFET with a reference potential of the reference voltage source, and a control circuit section for turning off the main MOSFET in case of the overcurrent condition. The device further comprises a group of pads allowing a test of the overcurrent detecting function by application of a test current much lower than an overcurrent. The pad group comprises a first pad for measuring the potential at the source of the mirror MOSFET, a second pad for measuring the reference potential and a third pad for detecting a change in the output of the comparator.
    • MOSFET集成电路器件具有主MOSFET,反射镜MOSFET,电流感测电阻器,参考电压源,用于通过将反射镜MOSFET的源极处的电位与参考电压的参考电位进行比较来检测过电流状态的比较器 源极和用于在过电流状态下关断主MOSFET的控制电路部分。 该装置还包括一组衬垫,其允许通过施加远低于过电流的测试电流来测试过电流检测功能。 焊盘组包括用于测量反射镜MOSFET源极处的电位的第一焊盘,用于测量参考电位的第二焊盘和用于检测比较器的输出变化的第三焊盘。