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1. 发明申请

US20080104567A1 APPARATUS AND METHOD FOR ALLOCATING COMPONENT, AND COMPUTER READABLE MEDIUM 审中-公开
标题翻译：用于分配组件的装置和方法以及计算机可读介质
公开(公告)号：US20080104567A1
公开(公告)日：2008-05-01
申请号：US11924820
申请日：2007-10-26
申请人： Shigeta Kuninobu , Keiichi Handa
发明人： Shigeta Kuninobu , Keiichi Handa
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： There is provided an apparatus that creates a component allocation plan for an electronic apparatus including first and second allocation layers in which components are allocated, including: a storage configured to store first and second component information indicating sizes of a plurality of first components and a plurality of second components to be allocated in the first and second allocation layer; an allocation order determiner configured to determine first and second allocation orders in which the first and second components are allocated for each layer; an allocation strategy determiner configured to determine first and second allocation strategies by which the first and second components are allocated, which are different each other; and a component allocating unit configured to allocate the first and second components in the first and second allocation layer in accordance with the first and second allocation orders and the first and second allocation strategies.
摘要翻译：提供了一种为包括分配组件的第一和第二分配层的电子设备创建组件分配计划的设备，包括：存储器，被配置为存储指示多个第一组件和多个组件的大小的第一组件信息和第二组件信息要分配在第一和第二分配层中的第二组件; 配置为确定为每个层分配第一和第二组件的第一和第二分配顺序的分配顺序确定器; 分配策略确定器，其被配置为确定第一和第二分配策略，第一和第二分配策略被分配，所述第一和第二分配策略彼此不同; 以及组件分配单元，被配置为根据第一和第二分配顺序以及第一和第二分配策略来分配第一和第二分配层中的第一和第二组件。

2. 发明申请

US20050065867A1 Demand-and-supply intervening system, demand-and-supply intervening method, and demand-and-supply intervening support program 审中-公开
标题翻译：需求供应干预制度，需求供应干预方式和需求供应干预支持方案
公开(公告)号：US20050065867A1
公开(公告)日：2005-03-24
申请号：US10896996
申请日：2004-07-23
申请人： Hideyuki Aisu , Keiichi Handa , Toshiaki Tanaka , Tomoshi Otsuki
发明人： Hideyuki Aisu , Keiichi Handa , Toshiaki Tanaka , Tomoshi Otsuki
IPC分类号： G06Q30/00 , G06F17/60
CPC分类号： G06Q30/08 , G06Q40/04
摘要： A demand-and-supply intervening system which supports determination of a demand-and-supply relationship between users in association with demand resources and supply resources between a plurality of users, comprises an entry acquisition unit for creating an entry set by collecting a plurality of entries each of which has a plurality of resources as demand/supply objects and a combinatorial condition to be satisfied between resources, and a candidate group determination unit for extracting a candidate group of entries so that all entries included in the candidate group satisfy combinatorial conditions included in each entry when extracting the candidate group having a plurality of entry which includes at least one entry designated as a base point, and determining the presence/absence of demand-and-supply relationships between demand and supply resources between entries which belong to the candidate group and demand-and-supply quantities.
摘要翻译：支持确定与多个用户之间的需求资源和供应资源之间的用户之间的需求与供给关系的需求供应中介系统，包括：入口获取单元，用于通过收集多个其中每个具有作为需求/供给对象的多个资源和要在资源之间满足的组合条件的条目;以及候选组确定单元，用于提取候选组的条目，使得包括在候选组中的所有条目满足包括的组合条件在提取具有指定为基点的至少一个条目的多个条目的候选组中的每个条目中，并且在属于候选者的条目之间确定需求与供给资源之间的供求关系的存在/不存在集团和供需数量。

3. 发明授权

US06275980B1 Programming method for concurrent programs and program supporting apparatus thereof 失效
标题翻译：并行程序的编程方法及其程序支持装置
公开(公告)号：US06275980B1
公开(公告)日：2001-08-14
申请号：US09112006
申请日：1998-07-08
申请人： Naoshi Uchihira , Shinichi Honiden , Akihiko Ohsuga , Toshibumi Seki , Yasuo Nagai , Keiichi Handa , Satoshi Ito , Nobuyuki Sawashima , Yasuyuki Tahara , Hideaki Shiotani
发明人： Naoshi Uchihira , Shinichi Honiden , Akihiko Ohsuga , Toshibumi Seki , Yasuo Nagai , Keiichi Handa , Satoshi Ito , Nobuyuki Sawashima , Yasuyuki Tahara , Hideaki Shiotani
IPC分类号： G06F945
CPC分类号： G06F11/3664 , G06F8/30 , G06F8/45 , G06F11/362 , G06F11/3696
摘要： An apparatus for supporting parallelization according to the invention is characterized by comprising a serialization unit for converting a first concurrent program having a concurrent structure into a sequential program capable of being sequentially executed, a debugging unit for debugging the sequential program and forming debugging information, and a concurrent program programming unit for performing parallelization of the debugged sequential program on the basis of the debugging information to convert the sequential program into a second concurrent program. With above configuration, the debugging unit includes a unit for introducing information associated with concurrency to the sequential program.
摘要翻译：根据本发明的用于支持并行化的装置的特征在于包括：串行化单元，用于将具有并行结构的第一并发程序转换成能够被顺序执行的顺序程序;调试单元，用于调试顺序程序并形成调试信息，以及并行程序编程单元，用于根据调试信息执行调试顺序程序的并行化，以将顺序程序转换为第二并发程序。通过上述配置，调试单元包括用于将与并发相关联的信息引入到顺序程序的单元。

4. 发明授权

US06598222B2 Programming method for concurrent programs and program supporting apparatus thereof 有权
标题翻译：并行程序的编程方法及其程序支持装置
公开(公告)号：US06598222B2
公开(公告)日：2003-07-22
申请号：US09842982
申请日：2001-04-27
申请人： Naoshi Uchihira , Shinichi Honiden , Akihiko Ohsuga , Toshibumi Seki , Yasuo Nagai , Keiichi Handa , Satoshi Ito , Nobuyuki Sawashima , Yasuyuki Tahara , Hideaki Shiotani
发明人： Naoshi Uchihira , Shinichi Honiden , Akihiko Ohsuga , Toshibumi Seki , Yasuo Nagai , Keiichi Handa , Satoshi Ito , Nobuyuki Sawashima , Yasuyuki Tahara , Hideaki Shiotani
IPC分类号： G06F944
CPC分类号： G06F11/3664 , G06F8/30 , G06F8/45 , G06F11/362 , G06F11/3696
摘要： An apparatus for supporting parallelization according to the invention is characterized by comprising a serialization unit for converting a first concurrent program having a concurrent structure into a sequential program capable of being sequentially executed, a debugging unit for debugging the sequential program and forming debugging information, and a concurrent program programming unit for performing parallelization of the debugged sequential program on the basis of the debugging information to convert the sequential program into a second concurrent program. With above configuration, the debugging unit includes a unit for introducing information associated with concurrency to the sequential program.
摘要翻译：根据本发明的用于支持并行化的装置的特征在于包括：串行化单元，用于将具有并行结构的第一并发程序转换成能够被顺序执行的顺序程序;调试单元，用于调试顺序程序并形成调试信息，以及并行程序编程单元，用于根据调试信息执行调试顺序程序的并行化，以将顺序程序转换为第二并发程序。通过上述配置，调试单元包括用于将与并发相关联的信息引入到顺序程序的单元。

5. 发明授权

US6067259A Method and device for repairing arrays with redundancy 失效
标题翻译：用冗余修复阵列的方法和设备
公开(公告)号：US6067259A
公开(公告)日：2000-05-23
申请号：US93729
申请日：1998-06-09
申请人： Keiichi Handa , Kazuhito Haruki
发明人： Keiichi Handa , Kazuhito Haruki
IPC分类号： G11C29/44 , G11C7/00 , G11C29/00
CPC分类号： G11C29/808
摘要： A fault repair method including the steps of providing second memory cells as spare lines for repairing faulty elements of first memory cells for storing data therein, setting virtual third memory cells with respect to a repair target including said first memory cells and the second memory cells, and repairing the faulty elements of the first memory cells and the second memory cells by using the virtual third cells.
摘要翻译：一种故障修复方法，包括以下步骤：提供第二存储器单元作为备用线，用于修复用于存储数据的第一存储器单元的故障元件，相对于包括所述第一存储单元和第二存储单元的修复目标设置虚拟第三存储器单元，以及通过使用所述虚拟第三单元来修复所述第一存储单元和所述第二存储单元的故障元件。

6. 发明授权

US5860009A Programming method for concurrent programs and program supporting apparatus thereof 失效
公开(公告)号：US5860009A
公开(公告)日：1999-01-12
申请号：US429782
申请日：1995-04-27
申请人： Naoshi Uchihira , Shinichi Honiden , Akihiko Ohsuga , Toshibumi Seki , Yasuo Nagai , Keiichi Handa , Satoshi Ito , Nobuyuki Sawashima , Yasuyuki Tahara , Hideaki Shiotani
发明人： Naoshi Uchihira , Shinichi Honiden , Akihiko Ohsuga , Toshibumi Seki , Yasuo Nagai , Keiichi Handa , Satoshi Ito , Nobuyuki Sawashima , Yasuyuki Tahara , Hideaki Shiotani
IPC分类号： G06F9/44 , G06F11/36 , G06F9/45
CPC分类号： G06F11/3664 , G06F11/362 , G06F11/3696 , G06F8/30 , G06F8/45
摘要： An apparatus for supporting parallelization according to the invention is characterized by comprising a serialization unit for converting a first concurrent program having a concurrent structure into a sequential program capable of being sequentially executed, a debugging unit for debugging the sequential program and forming debugging information, and a concurrent program programming unit for performing parallelization of the debugged sequential program on the basis of the debugging information to convert the sequential program into a second concurrent program. With above configuration, the debugging unit includes a unit for introducing information associated with concurrency to the sequential program.

7. 发明授权

US5465218A Element placement method and apparatus 失效
标题翻译：元件放置方法和装置
公开(公告)号：US5465218A
公开(公告)日：1995-11-07
申请号：US194389
申请日：1994-02-10
申请人： Keiichi Handa
发明人： Keiichi Handa
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An LSI element placement method of placing elements in accordance with an order in which branches are arranged, each branch being constituted by an element array included in a circuit diagram having first and second terminals, the method including a partial circuit extraction step of sequentially extracting data of a predetermined number of branches included in the circuit diagram from the first terminal side of the circuit diagram so as to overlap the data by a predetermined number, and an element placement step of performing an element placement operation based on a genetic algorithm in the extracted partial circuit data, thereby generating an element placement result including placement coordinate data of all elements included in the partial circuit data.
摘要翻译：一种LSI元件放置方法，按照分支排列的顺序放置元件，每个分支由包括在具有第一和第二端子的电路图中的元件阵列构成，该方法包括：顺序提取数据的部分电路提取步骤从电路图的第一端侧包括在电路图中的预定数量的分支，以使数据与预定数量重叠;以及元素放置步骤，基于提取的遗传算法执行元素放置操作部分电路数据，从而生成包括部分电路数据中包括的所有元素的放置坐标数据的元素放置结果。

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