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    • 8. 发明授权
    • Frame buffer memory for display
    • 帧缓冲存储器用于显示
    • US4980765A
    • 1990-12-25
    • US464214
    • 1990-01-12
    • Yoshimichi KudoShigeru Komatsu
    • Yoshimichi KudoShigeru Komatsu
    • G09G5/00G06F12/02G06T1/60G09G5/14G09G5/34G09G5/39G09G5/397
    • G09G5/14G09G5/397G09G2360/126
    • A frame buffer memory capable of storing video data for plural frames of pictures with memory areas irrelevant to the display being reduced to a minimum, which video data consist of a number of pixels unequal to a power of "2" in the vertical and horizontal directions, respectively. The frame buffer memory is realized by using multi-port video RAMs and includes a plurality of regions for display and auxiliary regions. The regions for display includes at least first and second display regions which partially overlap each other. The auxiliary regions store the video data contained in the overlapping portion (overlapping region) of the first and second display regions, the video data stored in the auxiliary region being transferred to the overlapping region as occasion requires.
    • 能够将与图像无关的存储区域的多帧图像的视频数据的帧缓冲存储器减少到最小,哪个视频数据由不同于垂直和水平方向上的“2”的功率的像素数组成 , 分别。 帧缓冲存储器是通过使用多端口视频RAM来实现的,并且包括用于显示和辅助区域的多个区域。 用于显示的区域至少包括彼此部分重叠的至少第一和第二显示区域。 辅助区域存储包含在第一和第二显示区域的重叠部分(重叠区域)中的视频数据,根据需要,存储在辅助区域中的视频数据被传送到重叠区域。
    • 10. 发明授权
    • Semiconductor device
    • 半导体器件
    • US4484212A
    • 1984-11-20
    • US335712
    • 1981-12-29
    • Shigeru KomatsuMichio NakamuraKatsuji Fujita
    • Shigeru KomatsuMichio NakamuraKatsuji Fujita
    • H01L27/04H01L21/768H01L21/822H01L23/522H01L23/58H01L27/08H01L29/84H01L23/48H01L27/02H01L29/44
    • H01L23/585H01L23/522H01L27/0802H01L2924/0002Y10S257/925Y10S73/04
    • A semiconductor device comprising a semiconductor substrate having at least two resistor elements, wherein said resistor elements have a specific resistance ratio relative to each other, an insulation layer formed on a major surface of said semiconductor substrate, a circuit wiring layer formed on said insulation layer covering a portion of said insulation layer which corresponds to at least one of said resistor elements, and a dummy wiring layer made of the same material as that of the circuit wiring layer and formed on the insulation layer covering that portion of said insulation layer which corresponds to the resistor element or elements not covered by said circuit wiring layer, and where the ratio of an overlapping area of one resistor element in said circuit wiring layer and an overlapping area of the other resistor element and said dummy wiring layer is equal to a resistance ratio of said resistor elements.
    • 一种半导体器件,包括具有至少两个电阻元件的半导体衬底,其中所述电阻元件相对于彼此具有比电阻比,形成在所述半导体衬底的主表面上的绝缘层,形成在所述绝缘层上的电路布线层 覆盖对应于所述电阻元件中的至少一个的所述绝缘层的一部分,以及由与所述电路布线层相同的材料制成的虚拟布线层,并形成在所述绝缘层上,覆盖所述绝缘层对应的部分 连接到所述电路布线层未被覆盖的电阻元件或元件,并且其中所述电路布线层中的一个电阻元件的重叠区域与所述另一个电阻元件与所述伪布线层的重叠区域的重叠面积之比等于电阻 所述电阻元件的比例。