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    • 4. 发明授权
    • Method of maximum likelihood decoding and digital information playback
apparatus
    • 最大似然解码方法和数字信息播放装置
    • US5719843A
    • 1998-02-17
    • US668178
    • 1996-06-21
    • Takeshi NakajimaShigeru FurumiyaYoshinari TakemuraKenji Koishi
    • Takeshi NakajimaShigeru FurumiyaYoshinari TakemuraKenji Koishi
    • G11B20/10H03M13/41G11B7/00
    • G11B20/10148G11B20/10009H03M13/41H03M13/4107H03M13/6331H03M13/6343
    • A digital information playback apparatus comprises A/D converter that converts a playback signal into digital data, a maximum likelihood decoder that decodes the quantized data output from the A/D converter to obtain the original digital information, and a timing signal extractor that generates a sampling clock used in the A/D converter, and wherein the maximum likelihood decoder detects the response characteristic of the record/playback system and obtains level fluctuations contained in the playback signal, based on the survival path obtained as a maximum likelihood decoding result, to control the expected multilevel equalized values used in the maximum likelihood decoder, the timing signal extractor obtains level fluctuations, based on the survival path obtained as a maximum likelihood decoding result, and obtains the component of the level fluctuations due to phase shifts of the sampling clock of the VCO to control the phase of the sampling clock of the VCO.
    • 一种数字信息播放装置,包括将重放信号转换为数字数据的A / D转换器,对从A / D转换器输出的量化数据进行解码以获得原始数字信息的最大似然解码器,以及生成 在A / D转换器中使用的采样时钟,其中最大似然解码器基于作为最大似然解码结果获得的生存路径,检测记录/重放系统的响应特性并获得包含在重放信号中的电平波动, 控制在最大似然解码器中使用的期望的多级均衡值,定时信号提取器基于作为最大似然解码结果获得的存活路径获得电平波动,并且获得由于采样时钟的相移引起的电平波动的分量 的VCO来控制VCO的采样时钟的相位。
    • 7. 发明授权
    • Optical disk system
    • 光盘系统
    • US5400315A
    • 1995-03-21
    • US165560
    • 1993-12-13
    • Kenji KoishiYoshinari TakemuraShigeru Furumiya
    • Kenji KoishiYoshinari TakemuraShigeru Furumiya
    • H04N5/85G11B7/00G11B7/004G11B20/10H04N5/92H04N9/79H04N9/82
    • H04N9/8216H04N9/7904
    • An analog-to-digital converter executes analog-to-digital conversion of a first analog video signal at a predetermined sampling frequency "fs". A time base converter converts a time base of an output signal from the analog-to-digital converter at a predetermined time base conversion frequency "ftci". A digital output signal from the time base converter is converted into a corresponding second analog video signal in response to a clock signal of a frequency corresponding to the frequency "ftci". The second analog video signal is converted into an FM video signal recorded on a video region of an optical disk. A binary audio digital signal is converted into a multi-level form digital audio signal. The binary audio digital signal has a data rate corresponding to the frequency "ftci". The multi-level form digital audio signal has a data rate "ftci/n" and 2.sup.n discrete amplitude levels where "n" denotes a predetermined integer. The multi-level form digital audio signal is converted into a corresponding analog audio signal in response to the clock signal of the frequency corresponding to the frequency "ftci". The analog audio signal is converted into an FM audio signal recorded on an audio region of the optical disk. A data signal generator generates a digital data signal at a data rate "ftci/m" where "m" denotes a predetermined integer. The digital data signal is converted into a corresponding analog data signal in response to the clock signal of the frequency corresponding to the frequency "ftci". The analog data signal is converted into an FM data signal recorded on a data region of the optical disk.
    • 模数转换器以预定的采样频率“fs”执行第一模拟视频信号的模数转换。 时基转换器以预定的时基转换频率“ftci”转换来自模数转换器的输出信号的时基。 响应于与频率“ftci”对应的频率的时钟信号,来自时基转换器的数字输出信号被转换成对应的第二模拟视频信号。 第二模拟视频信号被转换成记录在光盘的视频区域上的FM视频信号。 二进制音频数字信号被转换为多电平形式的数字音频信号。 二进制音频数字信号具有对应于频率“ftci”的数据速率。 多级形式数字音频信号具有数据速率“ftci / n”和2n个离散幅度电平,其中“n”表示预定的整数。 响应于对应于频率“ftci”的频率的时钟信号,多级形式的数字音频信号被转换成相应的模拟音频信号。 模拟音频信号被转换成记录在光盘的音频区域上的FM音频信号。 数据信号发生器以数据速率“ftci / m”生成数字数据信号,其中“m”表示预定的整数。 响应于对应于频率“ftci”的频率的时钟信号,将数字数据信号转换成对应的模拟数据信号。 模拟数据信号被转换成记录在光盘的数据区域上的FM数据信号。
    • 8. 发明授权
    • Synchronous clock generator and time-base error corrector
    • 同步时钟发生器和时基误差校正器
    • US5298998A
    • 1994-03-29
    • US982373
    • 1992-11-25
    • Shigeru FurumiyaYoshinari Takemura
    • Shigeru FurumiyaYoshinari Takemura
    • H04L7/033H04N5/06H04N5/932H04N5/945H04N5/956H04N5/04
    • H04N5/932H04N5/945
    • In a clock generator circuit, a zero hold circuit produces from a fixed clock signal a zero hold clock signal which is in phase with an external sync signal. A phase comparator circuit produces phase difference data indicating the phase difference between the external sync signal and an internal sync signal. A counter cleared by the external sync signal counts pulses of the zero hold clock signal to obtain count data. A memory receiving the phase difference data and the count data as its address input produces the internal sync signal when the count data is smaller than the number of pulses in one cycle of the external sync signal having no time-base variations, and a phase control signal determined by the phase difference data and the count data. A phase shifter shifts the phase of the zero hold clock according to the phase control signal to obtain a modified clock signal synchronized with the external sync signal.
    • 在时钟发生器电路中,零保持电路从固定时钟信号产生与外部同步信号同相的零保持时钟信号。 相位比较器电路产生指示外部同步信号和内部同步信号之间的相位差的相位差数据。 由外部同步信号清零的计数器对零保持时钟信号的脉冲进行计数以获得计数数据。 当计数数据小于没有时基偏差的外部同步信号的一个周期中的脉冲数时,接收相位差数据和计数数据作为其地址输入的存储器产生内部同步信号,并且相位控制 由相位差数据和计数数据确定的信号。 移相器根据相位控制信号移位零保持时钟的相位,以获得与外部同步信号同步的修改的时钟信号。