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1. 发明授权

US5093902A Memory control apparatus for accessing an image memory in cycle stealing fashion to read and write videotex signals 失效
标题翻译：用于访问周期中的图像存储器的存储器控制装置，用于读取和写入视频信号
公开(公告)号：US5093902A
公开(公告)日：1992-03-03
申请号：US652379
申请日：1991-02-07
申请人： Shigenori Tokumitsu
发明人： Shigenori Tokumitsu
IPC分类号： G09G5/00 , G09G1/16 , G09G5/39
CPC分类号： G09G5/001 , G09G2360/125 , G09G5/39
摘要： An operation of a CPU is defined by a predetermined clock. An image memory stores in or read-out image data to be displayed. A display controller connects between the CPU and the image memory, and receives a command from the CPU during an access period set by time-dividing a display period and for controlling a write or read operation of the image data with respect to the image memory. A timing signal generator generates a reference pulse for representing a relationship between the clock for defining the operation of the CPU and the access period. An operation state detector receives the reference pulse generated by the timing signal generator and an access control signal output from the CPU, and detects a state of the CPU with respect to the access period. A wait signal generator generates a wait signal to the CPU, in accordance with a detection result from the operation state detector.
摘要翻译： CPU的操作由预定时钟定义。图像存储器存储或读出要显示的图像数据。显示控制器连接在CPU和图像存储器之间，并且在通过分时显示周期设置的访问时段期间从CPU接收命令，并且用于控制图像数据相对于图像存储器的写或读操作。定时信号发生器产生用于表示用于定义CPU的操作的时钟和存取周期之间的关系的参考脉冲。操作状态检测器接收由定时信号发生器产生的参考脉冲和从CPU输出的访问控制信号，并检测CPU相对于访问周期的状态。等待信号发生器根据来自操作状态检测器的检测结果向CPU产生等待信号。

2. 发明授权

US4796221A Memory control device 失效
标题翻译：内存控制装置
公开(公告)号：US4796221A
公开(公告)日：1989-01-03
申请号：US844624
申请日：1986-03-27
申请人： Shigenori Tokumitsu
发明人： Shigenori Tokumitsu
IPC分类号： G06F13/16 , G06F12/00 , G09G5/00 , G09G5/36 , G09G5/39 , G09G5/395 , G06F13/40 , G06F3/00
CPC分类号： G09G5/39
摘要： A memory control device which is able to interface with any memory regardless of the address information format for reading out data stored therein. The memory control device includes an address generator for generating address information for reading out corresponding data from the memory device, a data processing circuit such as a microprocessor for processing the stored data, a first bus for transmitting the stored data from the memory device to the data processing circuit, a second bus for transmitting address information generated by the address generator to the memory device, a third bus for selectively transmitting either the stored data to the data processing circuit or transmitting address data to the memory device, a mode signal generator for generating a mode signal, and a control circuit connected between the mode signal generator and the third bus for controlling the selective data transmission of the third bus in response to the mode signal.
摘要翻译：一种存储器控制装置，其能够与任何存储器接口，而不管用于读出存储在其中的数据的地址信息格式。存储器控制装置包括：地址发生器，用于产生用于从存储器件读出相应数据的地址信息;数据处理电路，例如微处理器，用于处理存储的数据;第一总线，用于将存储的数据从存储器件发送到数据处理电路，用于将由地址发生器产生的地址信息发送到存储器件的第二总线，用于选择性地将存储的数据传送到数据处理电路或将地址数据发送到存储器件的第三总线;模式信号发生器，产生模式信号，以及连接在模式信号发生器和第三总线之间的控制电路，用于响应于模式信号控制第三总线的选择性数据传输。

3. 发明授权

US4788540A Raster scan image data display controller including means for reducing flickering 失效
标题翻译：栅格扫描图像数据显示控制器包括用于减少闪烁的装置
公开(公告)号：US4788540A
公开(公告)日：1988-11-29
申请号：US886428
申请日：1986-07-17
申请人： Shigenori Tokumitsu , Masaaki Nishiura
发明人： Shigenori Tokumitsu , Masaaki Nishiura
IPC分类号： H04N7/08 , G09G1/14 , G09G5/18 , G09G5/395 , H04N7/025 , H04N7/03 , H04N7/035 , H04N7/081 , G09G1/00
CPC分类号： G09G1/146 , G09G5/395 , Y10S348/91
摘要： A raster scan image data display controller including a means for reducing flickering comprises an image memory for storing image data items at horizontal and vertical display addresses corresponding to horizontal and vertical coordinates on an image display area, a read-out device for supplying the horizontal and vertical display addresses to the image memory and reading out the image data items from the image memory, a display device for interlaced displaying of the read-out image data on paired scanning lines of two types of fields which are to be formed by a raster scan, a timing control device for synchronizing the horizontal and vertical display addresses with the raster scan of the display device, and a timing switching device for permitting said paired scanning lines of two types of fields formed by the raster scan in association with a timing control by the timing control device, to be switched, so as to select a pair of scanning lines which are situated close to each other.
摘要翻译：包括用于减少闪烁的装置的光栅扫描图像数据显示控制器包括：图像存储器，用于存储与图像显示区域上的水平和垂直坐标对应的水平和垂直显示地址的图像数据项，用于提供水平的读出装置和垂直显示地址到图像存储器并从图像存储器中读出图像数据项;显示装置，用于在通过光栅扫描形成的两种场的成对扫描线上隔行显示读出的图像数据用于使水平和垂直显示地址与显示装置的光栅扫描同步的定时控制装置和用于允许通过光栅扫描形成的两种类型的场的所述成对扫描线与定时控制相关联的定时切换装置定时控制装置被切换，以选择彼此靠近的一对扫描线。

4. 发明授权

US4727361A Digital video encoder circuit 失效
标题翻译：数字视频编码器电路
公开(公告)号：US4727361A
公开(公告)日：1988-02-23
申请号：US10144
申请日：1987-02-02
申请人： Shigenori Tokumitsu
发明人： Shigenori Tokumitsu
IPC分类号： G09G1/28
CPC分类号： G09G1/285
摘要： A decoder decodes digital color information data from an input section into a predetermined number of pieces of color information consisting of specific color information and specific luminance information. A first converter converts the specific luminance information of each of the predetermined number of pieces of color information into a digital luminance signal component. A second converter converts the two color difference signals uniquely defined by the relationship between the specific color information and the specific luminance information of each of the predetermined number of pieces of information into a digital color difference signal component. A modulator digitally performs balanced modulation for the two color subcarrier components having phases shifted by 90 degrees from a color subcarrier component generator by using the digital color difference signal components, and outputs digital carrier chrominance signal components. An adder adds the digital carrier chrominance signal components from the modulator and the digital luminance signal component, and outputs digital video signal components. A third converter converts the digital video signal components into an analog waveform and outputs an analog video signal.
摘要翻译：解码器将数字彩色信息数据从输入部分解码为由特定颜色信息和特定亮度信息组成的预定数量的彩色信息。第一转换器将预定数量的彩色信息中的每一个的特定亮度信息转换为数字亮度信号分量。第二转换器将由特定颜色信息和每个预定数量的信息的特定亮度信息之间的关系唯一地定义的两个色差信号转换为数字色差信号分量。调制器通过使用数字色差信号分量对具有从彩色副载波分量发生器偏移了90度的相位的两个彩色副载波分量数字执行平衡调制，并输出数字载波色度信号分量。加法器将来自调制器和数字亮度信号分量的数字载波色度信号分量相加，并输出数字视频信号分量。第三转换器将数字视频信号分量转换为模拟波形并输出模拟视频信号。

5. 发明授权

US5266932A Vertical scrolling address generating device 失效
标题翻译：垂直滚动地址生成装置
公开(公告)号：US5266932A
公开(公告)日：1993-11-30
申请号：US572567
申请日：1990-08-27
申请人： Shigenori Tokumitsu
发明人： Shigenori Tokumitsu
IPC分类号： G06F3/14 , G06F3/048 , G09G5/34 , G09G1/06
CPC分类号： G09G5/346
摘要： This invention relates to an image display system for reading out image data stored in an image memory and displaying the image data on multiple image planes and the vertical scrolling operation can be independently effected for each of the image planes displayed on the multiple image plane display basis. That is, assuming that two image planes are displayed on upper and lower areas, display starting addresses lying in the vertical direction of the upper and lower image planes and stored in registers are loaded into a counter via a switch in a display period of the upper and lower image planes to generate addresses in the vertical direction of the upper and lower image planes. The vertical scrolling operation only for one of the upper and lower image planes can be effected by sequentially updating the display starting addresses lying in the vertical direction of the upper and lower image planes and held in one of the registers.
摘要翻译：本发明涉及一种用于读出存储在图像存储器中的图像数据并在多个图像平面上显示图像数据的图像显示系统，并且可以对在多个图像平面显示基础上显示的每个图像平面独立地执行垂直滚动操作。也就是说，假设在上部和下部区域上显示两个图像平面，在上部和下部图像平面的垂直方向上显示存储在寄存器中的显示起始地址在上部的显示周期中经由开关被加载到计数器中和较低的图像平面以在上和下图像平面的垂直方向上产生地址。可以通过依次更新位于上下图像平面的垂直方向上的显示开始地址并将其保存在一个寄存器中来实现仅对上下像平面之一的垂直滚动操作。

6. 发明授权

US4599702A Divider circuit for dividing n-bit binary data using decimal shifting and summation techniques 失效
标题翻译：使用小数位移和求和技术分割n位二进制数据的分频电路
公开(公告)号：US4599702A
公开(公告)日：1986-07-08
申请号：US525490
申请日：1983-08-22
申请人： Shigenori Tokumitsu
发明人： Shigenori Tokumitsu
IPC分类号： G06F7/52 , G06F7/535 , G09G5/02 , G09G5/18 , H04N7/025 , H04N7/03 , H04N7/035 , H04N7/08 , H04N7/081
CPC分类号： G06F7/535 , G06F2207/5354
摘要： A divider circuit for dividing n-bit binary data L.sub.n by a number m which is defined as m=2.sup.a -1 (a is a positive integer of 2 or more), wherein a division operation L.sub.n /m is developed into an infinite series given as: ##EQU1## for L.sub.(n-ba) =L.sub.n /2.sup.ba (where b is a positive integer).The divider circuit includes a first circuit responsive to the binary data L.sub.n, for sectioning a decimal part of each term of the infinite series in a unit of a-bit from a most significant bit of the decimal part, and for summing corresponding a-bit sectioned portions of decimal parts of all terms of the infinite series to generate summed decimal parts, a second circuit for discriminating a carry to an integer part of the binary data L.sub.n from the summed decimal parts, and a third circuit for adding the carry to a sum of integer parts of the binary data L.sub.n to provide divided data corresponding to L.sub.n /m.
摘要翻译：用于将n位二进制数据Ln分割为m = 2a-1（a为2以上的正整数）的数m的分频电路，其中分频运算Ln / m产生为给定的无限系列作为：对于L（n-ba）= Ln / 2ba（其中b是正整数）的。分频器电路包括响应于二进制数据Ln的第一电路，用于从小数部分的最高有效位以a位为单位分割无限序列的每个项的小数部分，并且用于将对应的一位无穷级数的所有项的十进制部分的分段部分，以产生相加的小数部分，用于从加法的小数部分将进位识别为二进制数据Ln的整数部分的第二电路和用于将进位加到二进制数据Ln的整数部分的和以提供对应于Ln / m的分割数据。

7. 发明授权

US4594516A Sampling pulse generator 失效
标题翻译：采样脉冲发生器
公开(公告)号：US4594516A
公开(公告)日：1986-06-10
申请号：US517743
申请日：1983-07-27
申请人： Shigenori Tokumitsu
发明人： Shigenori Tokumitsu
IPC分类号： H04N7/025 , H03K5/135 , H04N7/03 , H04N7/035 , H04N7/083 , H04N7/087 , H04N7/088 , H03K5/13 , H03L7/00
CPC分类号： H04N7/0352 , H03K5/135
摘要： A first 5-stage ring counter generates a signal having a frequency of (4/5)f.sub.SC by dividing a frequency 8f.sub.SC of a signal. A second 5-stage ring counter generates a signal having a frequency of (4/5)f.sub.SC by dividing a frequency of a signal obtained by inverting the signal of frequency 8f.sub.SC by an inverter. A first sampling pulse output circuit generates a first sampling pulse from an output signal from the first 5-stage ring counter. A second sampling pulse output circuit generates a second sampling pulse from an output signal from the second 5-stage ring counter. A phase correction circuit causes synchronization of the count operation of the first 5-stage ring counter with a clock run-in signal. This phase correction is performed by shifting the phase of the output from the first 5-stage ring counter in units of the period of the signal of frequency 8f.sub.SC. When this phase correction is completed, the output signal from the first 5-stage ring counter is synchronized with the clock run-in signal such that the output signal is delayed by between 0 and 35 nsec with respect to the phase of the clock run-in signal. A discrininator divides a range of 0 to 35 nsec into two discrimination periods of 17.5 nsec each. The discriminator then discriminates during which one of the two discrimination periods the output signal from the first 5-stage ring counter appears. The discriminator then controls a sampling pulse switching circuit in accordance with the discrimination result.
摘要翻译：第一级5级环形计数器通过除以信号的频率8fSC产生频率为（4/5）f SC的信号。第二个5级环形计数器通过将通过反相频率8fSC的信号获得的信号的频率除以逆变器来产生频率为（4/5）fSC的信号。第一采样脉冲输出电路根据来自第一5级环形计数器的输出信号产生第一采样脉冲。第二采样脉冲输出电路从第二5级环形计数器的输出信号产生第二采样脉冲。相位校正电路使得第一5级环形计数器的计数操作与时钟输入信号同步。通过以频率8fSC的信号的周期为单位来移位来自第一5级环形计数器的输出的相位来执行该相位校正。当该相位校正完成时，来自第一5级环形计数器的输出信号与时钟输入信号同步，使得输出信号相对于时钟运行相位的相位延迟0至35nsec，信号。一个判断器将0到35nsec的范围分成两个每个17.5nsec的辨别周期。然后，鉴别器鉴别两个识别周期中哪一个是来自第一5级环形计数器的输出信号。鉴别器然后根据鉴别结果控制采样脉冲切换电路。

8. 发明授权

US5479184A Videotex terminal system using CRT display and binary-type LCD display 失效
标题翻译： Videotex终端系统采用CRT显示和二进制液晶显示
公开(公告)号：US5479184A
公开(公告)日：1995-12-26
申请号：US366442
申请日：1994-12-30
申请人： Shigenori Tokumitsu
发明人： Shigenori Tokumitsu
IPC分类号： G09G5/00 , G06F3/147 , G09G5/02 , G09G5/40 , G09G3/02
CPC分类号： G06F3/1475
摘要： In a videotex terminal system, image data has a code frame and a photo frame, and each of these frames includes dot pattern data, foreground color data, background color data, and flashing data. This type of image data can be simultaneously displayed on both a cathode ray tube display (CRT) and a liquid crystal display (LCD). These two displays are not controlled independently of each other; rather, they are controlled in association with each other by a display control unit to eliminate the need to use a complicated software program in a central processing unit (CPU) and to reduce the number of hardware components required by the system. The display control unit is particularly advantageous in that is can easily discriminate the code frame and the photo frame from each other, and it enables the system to execute a reliable display operation.
摘要翻译：在视频终端系统中，图像数据具有代码帧和相框，并且这些帧中的每一个包括点图案数据，前景颜色数据，背景颜色数据和闪烁数据。这种类型的图像数据可以同时显示在阴极射线管显示器（CRT）和液晶显示器（LCD）两者上。这两个显示器不是彼此独立地控制; 相反，它们由显示控制单元彼此相关联地控制，以消除在中央处理单元（CPU）中使用复杂的软件程序的需要，并且减少系统所需的硬件组件的数量。显示控制单元特别有利的是，可以容易地将代码帧和相框彼此区分开，并且使得系统能够执行可靠的显示操作。

9. 发明授权

US4845662A Data processor employing run-length coding 失效
标题翻译：采用游程编码的数据处理器
公开(公告)号：US4845662A
公开(公告)日：1989-07-04
申请号：US077944
申请日：1987-07-27
申请人： Shigenori Tokumitsu
发明人： Shigenori Tokumitsu
IPC分类号： G06F12/00 , G06F3/153 , G06F9/22 , G06F12/02 , G06F13/00 , G06F13/28 , G06T9/00 , H03M7/46 , H04N7/035
CPC分类号： G06F13/00 , G06F13/28 , G06T9/005 , H03M7/46 , H04N7/035
摘要： A character data processor for a videotex or teletext system includes a microcomputer section, a self data processing unit and a read/write memory. A memory access period for the memory exists in one read/write cycle of character data packets. Data processing unit responds to a first pulse indicating the start of the memory access period and to a second pulse indicating the end of the memory access period. Data processing unit includes an address change circuit which stores initial address data and transfers address data stored therein to the memory according to a transfer pulse. The content of address data is changed by a change pulse. A data register relays data transferred between the microcomputer section and the memory. A generator circuit generates the transfer pulse, the change pulse and a clock pulse according to the generation of the first and second pulses and a detection signal. A detection circuit responds to prescribed data indicating the run length of character data. A detection circuit detects a number of times of data transfer between the microcomputer section and the memory according to the clock pulse, and generates the detection signal when the number of times of data transferring corresponds to the prescribed data.
摘要翻译：用于视频或图文电视系统的字符数据处理器包括微型计算机部分，自身数据处理单元和读/写存储器。在字符数据包的一个读/写周期中存在存储器的存储器访问周期。数据处理单元响应指示存储器访问周期开始的第一脉冲和指示存储器访问周期结束的第二脉冲。数据处理单元包括地址改变电路，其存储初始地址数据并根据传送脉冲将存储在其中的地址数据传送到存储器。地址数据的内容由改变脉冲改变。数据寄存器中继在微型计算机部分和存储器之间传输的数据。发电机电路根据第一和第二脉冲的产生和检测信号产生转移脉冲，变化脉冲和时钟脉冲。检测电路响应指定字符数据的行程长度的规定数据。检测电路根据时钟脉冲检测微型计算机部分与存储器之间的数据传输次数，并且当数据传送次数对应于规定数据时产生检测信号。

10. 发明授权

US4780708A Display control system 失效
标题翻译：显示控制系统
公开(公告)号：US4780708A
公开(公告)日：1988-10-25
申请号：US805901
申请日：1985-12-06
申请人： Shigenori Tokumitsu
发明人： Shigenori Tokumitsu
IPC分类号： H04N7/083 , G06F3/153 , G09G5/00 , G09G5/02 , G09G5/36 , G09G5/39 , G09G5/391 , H04N7/084 , H04N7/085 , G09G1/14
CPC分类号： G09G5/391 , G09G5/024 , G09G5/026
摘要： A predetermined display period is divided into a plurality of shorter display periods. Image data is stored in an image memory and read in accordance with a period for reading the data from the memory. An accessing period is also provided, and access to the memory is made when the addressing mode is being set in a mode register during the accessing period, whereby the data is displayed by raster scanning.
摘要翻译：预定的显示周期被分成多个较短的显示周期。图像数据存储在图像存储器中，并根据用于从存储器读取数据的周期进行读取。还提供访问周期，并且当在访问周期期间在模式寄存器中设置寻址模式时进行存储器的访问，从而通过光栅扫描来显示数据。

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