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1. 发明申请

US20100054069A1 MEMORY SYSTEM 有权
标题翻译：记忆系统
公开(公告)号：US20100054069A1
公开(公告)日：2010-03-04
申请号：US12251444
申请日：2008-10-14
申请人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
发明人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
IPC分类号： G11C7/00
CPC分类号： G06F12/0246 , G06F13/161 , G06F13/1673 , G06F2212/7206 , G11C7/1006
摘要： The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
摘要翻译：本发明提供了一种有助于提高伴随存储器访问的数据处理的效率的存储器系统。存储器系统具有可重写非易失性存储器，缓冲存储器和控制器。控制器响应于来自外部设备的访问请求控制控制器和外部设备之间的第一数据传输，控制器和非易失性存储器之间的第二数据传输以及控制器和缓冲存储器之间的第三数据传送，控制在第三次数据传送中从控制器传送到缓冲存储器，并以时间共享的方式从缓冲存储器传输到控制器，并且能够与第一次数据传送或第二数据传输并行执行时间分享的方式。

2. 发明授权

US07450457B2 Memory system comprising a controller managing independent data transfer between input-output terminal, synchronous dynamic random access memory, and flash memory 有权
标题翻译：存储器系统包括控制输入输出端子，同步动态随机存取存储器和闪存之间的独立数据传输的控制器
公开(公告)号：US07450457B2
公开(公告)日：2008-11-11
申请号：US11785177
申请日：2007-04-16
申请人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
发明人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
IPC分类号： G11C7/00
CPC分类号： G06F12/0246 , G06F13/161 , G06F13/1673 , G06F2212/7206 , G11C7/1006
摘要： A memory system contributes to improvement in efficiency of a data process accompanying a memory access. The memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
摘要翻译：存储器系统有助于提高伴随存储器访问的数据处理的效率。存储器系统具有可重写的非易失性存储器，缓冲存储器和控制器。控制器响应于来自外部设备的访问请求控制控制器和外部设备之间的第一数据传输，控制器和非易失性存储器之间的第二数据传输以及控制器和缓冲存储器之间的第三数据传送，控制在第三次数据传送中从控制器传送到缓冲存储器，并以时间共享的方式从缓冲存储器传输到控制器，并且能够与第一次数据传送或第二数据传输并行执行时间分享的方式。

3. 发明申请

US20070285997A1 Memory system 有权
标题翻译：内存系统
公开(公告)号：US20070285997A1
公开(公告)日：2007-12-13
申请号：US11785177
申请日：2007-04-16
申请人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
发明人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
IPC分类号： G11C11/34
CPC分类号： G06F12/0246 , G06F13/161 , G06F13/1673 , G06F2212/7206 , G11C7/1006
摘要： The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
摘要翻译：本发明提供了一种有助于提高伴随存储器访问的数据处理的效率的存储器系统。存储器系统具有可重写非易失性存储器，缓冲存储器和控制器。控制器响应于来自外部设备的访问请求控制控制器和外部设备之间的第一数据传输，控制器和非易失性存储器之间的第二数据传输以及控制器和缓冲存储器之间的第三数据传送，控制在第三次数据传送中从控制器传送到缓冲存储器，并以时间共享的方式从缓冲存储器传输到控制器，并且能够与第一次数据传送或第二数据传输并行执行时间分享的方式。

4. 发明申请

US20060036804A1 Nonvolatile memory system 审中-公开
公开(公告)号：US20060036804A1
公开(公告)日：2006-02-16
申请号：US11246074
申请日：2005-10-11
申请人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
发明人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
IPC分类号： G06F12/00
CPC分类号： G06F21/79 , G06F12/1425
摘要： To prevent stored information from being changed even at the occurrence of an abnormal condition in an upstream side of a system due to uncontrollable run of an OS. A nonvolatile storage means having data storage areas and management areas for them in units of predetermined physical addresses has an access protect definition table TLB in a predetermined physical address, and the table has access attribute information defining whether to permit or not access to the data storage areas in association with the physical addresses. The memory system itself possesses access attribute information defining whether to permit or not a write to and a read from the data storage areas in association with addresses to implement an access protect function for write and read. Therefore, the access protect function is maintained even if an abnormal condition occurs in a host device that manages the memory system or controls it as a peripheral circuit.

5. 发明申请

US20050162929A1 Memory system 有权
标题翻译：内存系统
公开(公告)号：US20050162929A1
公开(公告)日：2005-07-28
申请号：US11082859
申请日：2005-03-18
申请人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
发明人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
IPC分类号： G06F12/00 , G06F3/08 , G06F13/16 , G06F13/38 , G11C7/10 , G11C11/34
CPC分类号： G06F12/0246 , G06F13/161 , G06F13/1673 , G06F2212/7206 , G11C7/1006
摘要： The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
摘要翻译：本发明提供了一种有助于提高伴随存储器访问的数据处理的效率的存储器系统。存储器系统具有可重写非易失性存储器，缓冲存储器和控制器。控制器响应于来自外部设备的访问请求控制控制器和外部设备之间的第一数据传输，控制器和非易失性存储器之间的第二数据传输以及控制器和缓冲存储器之间的第三数据传送，控制在第三次数据传送中从控制器传送到缓冲存储器，并以时间共享的方式从缓冲存储器传输到控制器，并且能够与第一次数据传送或第二数据传输并行执行时间分享的方式。

6. 发明授权

US08036040B2 Memory system with improved efficiency of data transfer between host, buffer, and nonvolatile memory 有权
标题翻译：内存系统提高了主机，缓冲区和非易失性存储器之间的数据传输效率
公开(公告)号：US08036040B2
公开(公告)日：2011-10-11
申请号：US12251444
申请日：2008-10-14
申请人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
发明人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
IPC分类号： G11C16/06
CPC分类号： G06F12/0246 , G06F13/161 , G06F13/1673 , G06F2212/7206 , G11C7/1006
摘要： The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
摘要翻译：本发明提供了一种有助于提高伴随存储器访问的数据处理的效率的存储器系统。存储器系统具有可重写非易失性存储器，缓冲存储器和控制器。控制器响应于来自外部设备的访问请求控制控制器和外部设备之间的第一数据传输，控制器和非易失性存储器之间的第二数据传输以及控制器和缓冲存储器之间的第三数据传送，控制在第三次数据传送中从控制器传送到缓冲存储器，并以时间共享的方式从缓冲存储器传输到控制器，并且能够与第一次数据传送或第二数据传输并行执行时间分享的方式。

7. 发明授权

US07206233B2 Memory system with parallel data transfer between host, buffer and flash memory 有权
标题翻译：主机，缓冲器和闪存之间并行数据传输的内存系统
公开(公告)号：US07206233B2
公开(公告)日：2007-04-17
申请号：US11082859
申请日：2005-03-18
申请人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
发明人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
IPC分类号： G11C7/10
CPC分类号： G06F12/0246 , G06F13/161 , G06F13/1673 , G06F2212/7206 , G11C7/1006
摘要： A memory system is provided which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
摘要翻译：提供了一种存储系统，其有助于提高伴随存储器访问的数据处理的效率。存储器系统具有可重写非易失性存储器，缓冲存储器和控制器。控制器响应于来自外部设备的访问请求控制控制器和外部设备之间的第一数据传输，控制器和非易失性存储器之间的第二数据传输以及控制器和缓冲存储器之间的第三数据传送，控制在第三次数据传送中从控制器传送到缓冲存储器，并以时间共享的方式从缓冲存储器传输到控制器，并且能够与第一次数据传送或第二数据传输并行执行时间分享的方式。

8. 发明授权

US06882568B2 Memory system with improved efficiency of data transfer between host, buffer and nonvolatile memory 有权
标题翻译：内存系统提高主机，缓冲区和非易失性存储器之间的数据传输效率
公开(公告)号：US06882568B2
公开(公告)日：2005-04-19
申请号：US10404547
申请日：2003-04-02
申请人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
发明人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
IPC分类号： G06F12/00 , G06F3/08 , G06F13/16 , G06F13/38 , G11C7/10 , G11C14/00 , G11C7/00 , G06F3/00 , G06F13/12
CPC分类号： G06F12/0246 , G06F13/161 , G06F13/1673 , G06F2212/7206 , G11C7/1006
摘要： The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
摘要翻译：本发明提供了一种有助于提高伴随存储器访问的数据处理的效率的存储器系统。存储器系统具有可重写非易失性存储器，缓冲存储器和控制器。控制器响应于来自外部设备的访问请求控制控制器和外部设备之间的第一数据传输，控制器和非易失性存储器之间的第二数据传输以及控制器和缓冲存储器之间的第三数据传送，控制在第三次数据传送中从控制器传送到缓冲存储器，并以时间共享的方式从缓冲存储器传输到控制器，并且能够与第一次数据传送或第二数据传输并行执行时间分享的方式。

9. 发明授权

US06744692B2 Memory system's improvement in efficiency of data process between host, buffer memory and nonvolatile memory 有权
标题翻译：内存系统提高主机，缓冲存储器和非易失性存储器之间的数据处理效率
公开(公告)号：US06744692B2
公开(公告)日：2004-06-01
申请号：US10341367
申请日：2003-01-14
申请人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
发明人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
IPC分类号： G11C800
CPC分类号： G06F12/0246 , G06F13/161 , G06F13/1673 , G06F2212/7206 , G11C7/1006
摘要： The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
摘要翻译：本发明提供了一种有助于提高伴随存储器访问的数据处理的效率的存储器系统。存储器系统具有可重写非易失性存储器，缓冲存储器和控制器。控制器响应于来自外部设备的访问请求控制控制器和外部设备之间的第一数据传输，控制器和非易失性存储器之间的第二数据传输以及控制器和缓冲存储器之间的第三数据传送，控制在第三次数据传送中从控制器传送到缓冲存储器，并以时间共享的方式从缓冲存储器传输到控制器，并且能够与第一次数据传送或第二数据传输并行执行时间分享的方式。

10. 发明申请

US20120176842A1 Memory System 审中-公开
标题翻译：内存系统
公开(公告)号：US20120176842A1
公开(公告)日：2012-07-12
申请号：US13270224
申请日：2011-10-10
申请人： SHIGEMASA SHIOTA , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
发明人： SHIGEMASA SHIOTA , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
IPC分类号： G11C16/04
CPC分类号： G06F12/0246 , G06F13/161 , G06F13/1673 , G06F2212/7206 , G11C7/1006
摘要： The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
摘要翻译：本发明提供了一种有助于提高伴随存储器访问的数据处理的效率的存储器系统。存储器系统具有可重写非易失性存储器，缓冲存储器和控制器。控制器响应于来自外部设备的访问请求控制控制器和外部设备之间的第一数据传输，控制器和非易失性存储器之间的第二数据传输以及控制器和缓冲存储器之间的第三数据传送，控制在第三次数据传送中从控制器传送到缓冲存储器，并以时间共享的方式从缓冲存储器传输到控制器，并且能够与第一次数据传送或第二数据传输并行执行时间分享的方式。

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