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1. 发明授权

US06992021B2 Method for forming a silicon nitride layer 有权
标题翻译：形成氮化硅层的方法
公开(公告)号：US06992021B2
公开(公告)日：2006-01-31
申请号：US10620518
申请日：2003-07-16
申请人： Shian-Jyh Lin , Hai-Han Hung , Chung-Yuan Lee
发明人： Shian-Jyh Lin , Hai-Han Hung , Chung-Yuan Lee
IPC分类号： H01L21/39 , H01L21/469
CPC分类号： H01L29/66181 , C23C14/0652 , C23C14/48 , H01L21/26506 , H01L21/3185
摘要： A method of forming a silicon nitride layer. The method comprises providing a substrate having a silicon surface thereon, performing an ion implant process on the silicon surface, implanting nitrogen atoms into the silicon surface, and performing a thermal nitridation process and forming a silicon nitride layer on the substrate, wherein the silicon nitride layer comprises the silicon nitride formed on the silicon surface by reaction of the silicon surface with the nitrogen atoms contained therein.
摘要翻译：一种形成氮化硅层的方法。该方法包括提供其上具有硅表面的衬底，在硅表面上执行离子注入工艺，将氮原子注入到硅表面中，以及执行热氮化工艺并在衬底上形成氮化硅层，其中氮化硅层包括通过硅表面与其中包含的氮原子的反应在硅表面上形成的氮化硅。

2. 发明授权

US06417064B1 Method for treating the surface of a deep trench 有权
标题翻译：处理深沟槽表面的方法
公开(公告)号：US06417064B1
公开(公告)日：2002-07-09
申请号：US09846302
申请日：2001-05-02
申请人： Shian-Jyh Lin , Hai-Han Hung
发明人： Shian-Jyh Lin , Hai-Han Hung
IPC分类号： H01L2120
CPC分类号： H01L27/1087 , H01L21/2022 , H01L21/26506 , H01L21/26586
摘要： A method of treating the surface of a deep trench is disclosed. After forming a deep trench in a silicon substrate, the silicon substrate near the surfaces of the deep trench is treated to become amorphous. An annealing process is executed to make the amorphous silicon layer recrystallize into its original lattice arrangement, so as to reduce lattice defects in the surface of the deep trench.
摘要翻译：公开了一种处理深沟槽表面的方法。在硅衬底中形成深沟槽之后，深沟槽表面附近的硅衬底被处理成非晶态。执行退火处理以使非晶硅层重结晶成其原始晶格布置，以便减少深沟槽表面中的晶格缺陷。

3. 发明授权

US08697316B2 Hard mask spacer structure and fabrication method thereof 有权
标题翻译：硬掩模间隔结构及其制造方法
公开(公告)号：US08697316B2
公开(公告)日：2014-04-15
申请号：US13492934
申请日：2012-06-11
申请人： Ya-Chih Wang , Hai-Han Hung , Wen-Chieh Wang
发明人： Ya-Chih Wang , Hai-Han Hung , Wen-Chieh Wang
IPC分类号： G03F1/38
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/31144
摘要： A hard mask spacer structure includes a first spacer on a device layer, the first spacer defining a plurality of hole patterns and at least an asteriated hole pattern between the hole patterns; and a second spacer on the first spacer and inlaid into the asteriated hole pattern, thereby rounding the asteriated hole pattern.
摘要翻译：硬掩模间隔结构包括在器件层上的第一间隔物，第一间隔物限定多个孔图案，并且在孔图案之间至少形成一个空心孔图案; 以及在第一间隔件上的第二间隔件，并嵌入到空心孔图案中，从而使空心孔图案四舍五入。

4. 发明申请

US20140054720A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEROF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140054720A1
公开(公告)日：2014-02-27
申请号：US13594726
申请日：2012-08-24
申请人： Yu-Wei Liang , Hai-Han Hung , Pei-Chi Wu
发明人： Yu-Wei Liang , Hai-Han Hung , Pei-Chi Wu
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/28035 , H01L21/82345 , H01L21/823842 , H01L29/4925 , H01L29/66575
摘要： A method for fabricating a semiconductor device is provided. A first polysilicon layer of a first conductivity type is provided on a substrate having first and second active regions. An ion implantation process is performed in the polysilicon layer corresponding to the second active region by using a dopant of a second conductivity type opposite to the first conductivity type, and silane plasma is introduced during the ion implantation process to form a second polysilicon layer thereon and convert the first conductivity type of the first polysilicon layer corresponding to the second active region to the second conductivity type. The first and second polysilicon layers are patterned to form a first gate layer corresponding to the first active region and a second gate layer corresponding to the second active region. A semiconductor device is also provided.
摘要翻译：提供一种制造半导体器件的方法。第一导电类型的第一多晶硅层设置在具有第一和第二有源区的衬底上。通过使用与第一导电类型相反的第二导电类型的掺杂剂在与第二有源区对应的多晶硅层中进行离子注入工艺，并且在离子注入工艺期间引入硅烷等离子体以在其上形成第二多晶硅层，将与第二有源区对应的第一多晶硅层的第一导电类型转换为第二导电类型。图案化第一和第二多晶硅层以形成对应于第一有源区的第一栅极层和对应于第二有源区的第二栅极层。还提供了半导体器件。

5. 发明授权

US09029255B2 Semiconductor device and fabrication method therof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US09029255B2
公开(公告)日：2015-05-12
申请号：US13594726
申请日：2012-08-24
申请人： Yu-Wei Liang , Hai-Han Hung , Pei-Chi Wu
发明人： Yu-Wei Liang , Hai-Han Hung , Pei-Chi Wu
IPC分类号： H01L21/4763 , H01L21/8234 , H01L21/8238 , H01L21/28 , H01L29/49 , H01L29/66 , H01L29/08
CPC分类号： H01L29/0847 , H01L21/28035 , H01L21/82345 , H01L21/823842 , H01L29/4925 , H01L29/66575
摘要： A method for fabricating a semiconductor device is provided. A first polysilicon layer of a first conductivity type is provided on a substrate having first and second active regions. An ion implantation process is performed in the polysilicon layer corresponding to the second active region by using a dopant of a second conductivity type opposite to the first conductivity type, and silane plasma is introduced during the ion implantation process to form a second polysilicon layer thereon and convert the first conductivity type of the first polysilicon layer corresponding to the second active region to the second conductivity type. The first and second polysilicon layers are patterned to form a first gate layer corresponding to the first active region and a second gate layer corresponding to the second active region. A semiconductor device is also provided.
摘要翻译：提供一种制造半导体器件的方法。第一导电类型的第一多晶硅层设置在具有第一和第二有源区的衬底上。通过使用与第一导电类型相反的第二导电类型的掺杂剂在与第二有源区对应的多晶硅层中进行离子注入工艺，并且在离子注入工艺期间引入硅烷等离子体以在其上形成第二多晶硅层，将与第二有源区对应的第一多晶硅层的第一导电类型转换为第二导电类型。图案化第一和第二多晶硅层以形成对应于第一有源区的第一栅极层和对应于第二有源区的第二栅极层。还提供了半导体器件。

6. 发明申请

US20130330660A1 HARD MASK SPACER STRUCTURE AND FABRICATION METHOD THEREOF 有权
标题翻译：硬掩模间隔结构及其制造方法
公开(公告)号：US20130330660A1
公开(公告)日：2013-12-12
申请号：US13492934
申请日：2012-06-11
申请人： Ya-Chih Wang , Hai-Han Hung , Wen-Chieh Wang
发明人： Ya-Chih Wang , Hai-Han Hung , Wen-Chieh Wang
IPC分类号： G03F1/00 , G03F1/46
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/31144
摘要： A hard mask spacer structure includes a first spacer on a device layer, the first spacer defining a plurality of hole patterns and at least an asteriated hole pattern between the hole patterns; and a second spacer on the first spacer and inlaid into the asteriated hole pattern, thereby rounding the asteriated hole pattern.
摘要翻译：硬掩模间隔结构包括在器件层上的第一间隔物，第一间隔物限定多个孔图案，并且在孔图案之间至少形成一个空心孔图案; 以及在第一间隔件上的第二间隔件，并嵌入到空心孔图案中，从而使空心孔图案四舍五入。

7. 发明授权

US07696075B2 Method of fabricating semiconductor device having a recess channel structure therein 有权
标题翻译：制造其中具有凹槽通道结构的半导体器件的方法
公开(公告)号：US07696075B2
公开(公告)日：2010-04-13
申请号：US12055298
申请日：2008-03-25
申请人： Chien-An Yu , Te-Yin Chen , Hai-Han Hung
发明人： Chien-An Yu , Te-Yin Chen , Hai-Han Hung
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/78 , H01L29/66621
摘要： A method of fabricating a semiconductor device having a recess channel structure is provided. A first recess is formed in a substrate. A liner and a filling layer are formed in the first recess. A portion of the substrate adjacent to the first recess and a portion of the liner and the filling layer are removed to form trenches. An insulation layer fills the trenches to form isolation structures. The filling layer is removed, using the liner as an etching stop layer, to expose the insulation layer. A portion of the exposed insulation layer is removed to form a second recess having divots adjacent to the sidewalls of the substrate. The liner is removed. A dielectric layer and a gate are formed over the substrate covering the second recess. Source and drain regions are formed in the substrate adjacent to the second recess.
摘要翻译：提供一种制造具有凹槽通道结构的半导体器件的方法。在基板上形成第一凹部。衬垫和填充层形成在第一凹部中。与第一凹部相邻的衬底的一部分和衬垫的一部分和填充层被去除以形成沟槽。绝缘层填充沟槽以形成隔离结构。使用衬垫作为蚀刻停止层去除填充层，以露出绝缘层。暴露的绝缘层的一部分被去除以形成具有与衬底的侧壁相邻的凸起的第二凹部。衬里被移除。介电层和栅极形成在覆盖第二凹槽的衬底上。源极和漏极区域形成在与第二凹部相邻的衬底中。

8. 发明授权

US07666792B2 Method for fabricating a deep trench in a substrate 有权
标题翻译：在衬底中制造深沟槽的方法
公开(公告)号：US07666792B2
公开(公告)日：2010-02-23
申请号：US12035443
申请日：2008-02-22
申请人： Chung-Yen Chou , Hai-Han Hung , Teng-Wang Huang , Shin-Yu Nieh
发明人： Chung-Yen Chou , Hai-Han Hung , Teng-Wang Huang , Shin-Yu Nieh
IPC分类号： H01L21/311
CPC分类号： H01L21/3086 , H01L27/1087 , H01L29/66181
摘要： The invention provides a method for forming a deep trench in a substrate. A sacrificial layer and a liner layer are first used to define the deep trench pattern. The sacrificial layer is then replaced with a silicon glass layer. A thick mask layer includes the silicon glass layer, the liner layer and a silicon nitride layer is formed on the substrate. Through an opening of the thick mask layer, a deep trench is etched into the substrate.
摘要翻译：本发明提供了一种在衬底中形成深沟槽的方法。首先使用牺牲层和衬垫层来限定深沟槽图案。然后用硅玻璃层代替牺牲层。厚掩模层包括硅玻璃层，衬底层和氮化硅层形成在衬底上。通过厚掩模层的开口，将深沟槽蚀刻到衬底中。

9. 发明申请

US20090130853A1 METHOD FOR FABRICATING A DEEP TRENCH IN A SUBSTRATE 有权
标题翻译：在基板上制作深层TRENCH的方法
公开(公告)号：US20090130853A1
公开(公告)日：2009-05-21
申请号：US12035443
申请日：2008-02-22
申请人： Chung-Yen Chou , Hai-Han Hung , Teng-Wang Huang , Shin-Yu Nieh
发明人： Chung-Yen Chou , Hai-Han Hung , Teng-Wang Huang , Shin-Yu Nieh
IPC分类号： H01L21/311
CPC分类号： H01L21/3086 , H01L27/1087 , H01L29/66181
摘要： The invention provides a method for forming a deep trench in a substrate. A sacrificial layer and a liner layer are first used to define the deep trench pattern. The sacrificial layer is then replaced with a silicon glass layer. A thick mask layer includes the silicon glass layer, the liner layer and a silicon nitride layer is formed on the substrate. Through an opening of the thick mask layer, a deep trench is etched into the substrate.
摘要翻译：本发明提供了一种在衬底中形成深沟槽的方法。首先使用牺牲层和衬垫层来限定深沟槽图案。然后用硅玻璃层代替牺牲层。厚掩模层包括硅玻璃层，衬底层和氮化硅层形成在衬底上。通过厚掩模层的开口，将深沟槽蚀刻到衬底中。

10. 发明授权

US08216946B2 Patterning method 有权
标题翻译：图案化方法
公开(公告)号：US08216946B2
公开(公告)日：2012-07-10
申请号：US12490311
申请日：2009-06-23
申请人： Wei-Cheng Shiu , Hai-Han Hung , Ya-Chih Wang , Chien-Mao Liao , Shing-Yih Shih
发明人： Wei-Cheng Shiu , Hai-Han Hung , Ya-Chih Wang , Chien-Mao Liao , Shing-Yih Shih
IPC分类号： H01L21/302
CPC分类号： H01L21/0337 , H01L21/0338
摘要： A patterning method has a mask layer and undoped patterns sequentially formed on a target layer. A doping process is performed to surfaces of the undoped patterns to form doped patterns from the surfaces of the undoped patterns. A material is filled in the gaps between the doped patterns. A portion of the doped patterns are then removed to expose the top surfaces of the remaining undoped patterns. The material and the exposed undoped patterns are removed. A portion of the mask layer is removed using the remaining doped patterns as a mask to form a first pattern on the mask layer. A portion of the target layer is removed using the mask layer having the first pattern thereon as a mask so as to form on the target layer a second pattern complementary to the first pattern.
摘要翻译：图案化方法具有顺序形成在目标层上的掩模层和未掺杂图案。对未掺杂图案的表面进行掺杂工艺以从未掺杂图案的表面形成掺杂图案。材料填充在掺杂图案之间的间隙中。然后去除部分掺杂图案以露出剩余未掺杂图案的顶表面。材料和暴露的未掺杂图案被去除。使用剩余的掺杂图案作为掩模去除掩模层的一部分，以在掩模层上形成第一图案。使用其上具有第一图案的掩模层作为掩模去除目标层的一部分，以在目标层上形成与第一图案互补的第二图案。

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