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    • 1. 发明授权
    • Inspection plan optimization based on layout attributes and process variance
    • 基于布局属性和过程差异的检验计划优化
    • US07739065B1
    • 2010-06-15
    • US11761455
    • 2007-06-12
    • Sherry F. LeeKenneth R. HarrisDavid Joseph
    • Sherry F. LeeKenneth R. HarrisDavid Joseph
    • G01N17/02
    • G01R31/2894
    • Methods for determining customized defect detection inspection plans are provided. One method includes fabricating a test chip and generating test chip data from the fabricated test chip. Then, defining systematic signatures from the generated test chip data and identifying a yield relevant systematic signature from the defined systematic signatures. The method includes identifying a layout pattern associated with the yield relevant systematic signature and locating the identified layout pattern on a process module layer of a product chip. Further, the method includes defining a customized defect detection inspection or metrology methodology for detecting systematic defects on the process module layer based on the identified layout pattern associated with the yield relevant systematic signature.
    • 提供了确定定制缺陷检测检测计划的方法。 一种方法包括制造测试芯片并从制造的测试芯片产生测试芯片数据。 然后,从生成的测试芯片数据中定义系统签名,并根据定义的系统签名识别产量相关的系统签名。 该方法包括识别与产量相关系统签名相关联的布局模式,并将所识别的布局图案定位在产品芯片的处理模块层上。 此外,该方法包括基于与屈服相关系统签名相关联的所识别的布局模式来定义用于检测过程模块层上的系统缺陷的定制缺陷检测检验或度量方法。