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    • 5. 发明授权
    • Programmable clock trunk architecture
    • 可编程时钟中继架构
    • US06380788B1
    • 2002-04-30
    • US09853179
    • 2001-05-09
    • Chen-Teng FanJyh-Herng WangYu-Wen TsaiPeng-Chuan Huang
    • Chen-Teng FanJyh-Herng WangYu-Wen TsaiPeng-Chuan Huang
    • H03K300
    • H03K19/1774G06F1/10H03K5/15013H03K19/1778
    • A clock architecture including a clock source, a multi-phase clock signal generator, a control bus, a number of clock signal lines, and at least one circuit block. The clock source generates a global clock signal, which is then transferred to the multi-phase clock signal generator connected to the clock source. Upon receipt of global clock signal, the multi-phase clock signal generator, which is connected to a control bus, generates clock signals of different phases according to the signals from the control bus. Each of the clock signal branches transfers one of the clock signals of different phases, wherein each of the clock signal branches is individually connected to the circuit block through an electrical switch. Only one switch is at an on state at one time, so that the clock signal of a corresponding phase is transferred to the circuit block. The driving forces applied on the clock buffer connected to the clock source and the clock buffers on the branches are adjustable for reducing clock skew. Alternately, programmable delay buffers can be used for achieving the same goal.
    • 一种时钟架构,包括时钟源,多相时钟信号发生器,控制总线,多个时钟信号线以及至少一个电路块。 时钟源产生一个全局时钟信号,然后传输到连接到时钟源的多相时钟信号发生器。 在接收到全局时钟信号时,连接到控制总线的多相时钟信号发生器根据来自控制总线的信号产生不同相位的时钟信号。 每个时钟信号分支传送不同相位的时钟信号中的一个,其中每个时钟信号分支通过电开关单独连接到电路块。 一次只有一个开关处于导通状态,使相应相位的时钟信号传送到电路块。 连接到时钟源的时钟缓冲器和分支上的时钟缓冲器的驱动力可调,以减少时钟偏移。 或者,可以使用可编程延迟缓冲器来实现相同的目标。