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1. 发明申请

US20150269100A1 INTERFACE FOR STORAGE DEVICE ACCESS OVER MEMORY BUS 有权
标题翻译：用于存储器存储器的接口通过存储器总线访问
公开(公告)号：US20150269100A1
公开(公告)日：2015-09-24
申请号：US14731183
申请日：2015-06-04
申请人： Shekoufeh Qawami , Rajesh Sundaram , David J. Zimmerman , Robert W. Faber
发明人： Shekoufeh Qawami , Rajesh Sundaram , David J. Zimmerman , Robert W. Faber
IPC分类号： G06F13/28 , G06F12/02 , G06F13/42 , G11C7/22 , G06F1/12 , G06F13/16
CPC分类号： G06F13/28 , G06F1/12 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/385 , G06F13/409 , G06F13/42 , G06F2212/7201 , G06F2212/7203 , G11C7/222 , H04L5/00 , H04L7/00 , Y02D10/14 , Y02D10/151
摘要： A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.
摘要翻译：通过存储器总线访问非易失性存储器或存储器件。存储器总线具有通常用于易失性存储器件的电接口。耦合到总线的控制器向非易失性存储器件发送同步数据访问命令，并且基于来自非易失性存储器件的回复的期望定时从设备总线读取响应。控制器基于何时发送命令和非易失性存储器件的特性来确定预期时序。控制器可能不需要存储器总线上可用的所有电信号线，并且可以通过不同的电信号线组向不同组的非易失性存储器件发出数据访问命令。存储器总线可以可用并且被配置用于与存储器控制器和易失性存储器设备或存储控制器和非易失性存储器设备一起使用。

2. 发明授权

US08607089B2 Interface for storage device access over memory bus 有权
公开(公告)号：US08607089B2
公开(公告)日：2013-12-10
申请号：US13111839
申请日：2011-05-19
申请人： Shekoufeh Qawami , Rajesh Sundaram , David J. Zimmerman , Robert W. Faber
发明人： Shekoufeh Qawami , Rajesh Sundaram , David J. Zimmerman , Robert W. Faber
IPC分类号： G06F1/12 , G06F13/42 , H04L5/00 , H04L7/00
CPC分类号： G06F13/28 , G06F1/12 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/385 , G06F13/409 , G06F13/42 , G06F2212/7201 , G06F2212/7203 , G11C7/222 , H04L5/00 , H04L7/00 , Y02D10/14 , Y02D10/151
摘要： A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.

3. 发明申请

US20120297231A1 Interface for Storage Device Access Over Memory Bus 有权
标题翻译：通过内存总线访问存储设备的接口
公开(公告)号：US20120297231A1
公开(公告)日：2012-11-22
申请号：US13111839
申请日：2011-05-19
申请人： Shekoufeh Qawami , Rajesh Sundaram , David J. Zimmerman , Robert W. Faber
发明人： Shekoufeh Qawami , Rajesh Sundaram , David J. Zimmerman , Robert W. Faber
IPC分类号： G06F1/12
CPC分类号： G06F13/28 , G06F1/12 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/385 , G06F13/409 , G06F13/42 , G06F2212/7201 , G06F2212/7203 , G11C7/222 , H04L5/00 , H04L7/00 , Y02D10/14 , Y02D10/151
摘要： A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.
摘要翻译：通过存储器总线访问非易失性存储器或存储器件。存储器总线具有通常用于易失性存储器件的电接口。耦合到总线的控制器向非易失性存储器件发送同步数据访问命令，并且基于来自非易失性存储器件的回复的期望定时从设备总线读取响应。控制器基于何时发送命令和非易失性存储器件的特性来确定预期时序。控制器可能不需要存储器总线上可用的所有电信号线，并且可以通过不同的电信号线组向不同组的非易失性存储器件发出数据访问命令。存储器总线可以可用并且被配置用于与存储器控制器和易失性存储器设备或存储控制器和非易失性存储器设备一起使用。

4. 发明申请

US20140075107A1 INTERFACE FOR STORAGE DEVICE ACCESS OVER MEMORY BUS 有权
标题翻译：用于存储器存储器的接口通过存储器总线访问
公开(公告)号：US20140075107A1
公开(公告)日：2014-03-13
申请号：US14075765
申请日：2013-11-08
申请人： Shekoufeh Qawami , Rajesh Sundaram , David J. Zimmerman , Robert W. Faber
发明人： Shekoufeh Qawami , Rajesh Sundaram , David J. Zimmerman , Robert W. Faber
IPC分类号： G11C7/22
CPC分类号： G06F13/28 , G06F1/12 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/385 , G06F13/409 , G06F13/42 , G06F2212/7201 , G06F2212/7203 , G11C7/222 , H04L5/00 , H04L7/00 , Y02D10/14 , Y02D10/151
摘要： A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.
摘要翻译：通过存储器总线访问非易失性存储器或存储器件。存储器总线具有通常用于易失性存储器件的电接口。耦合到总线的控制器向非易失性存储器件发送同步数据访问命令，并且基于来自非易失性存储器件的回复的期望定时从设备总线读取响应。控制器基于何时发送命令和非易失性存储器件的特性来确定预期时序。控制器可能不需要存储器总线上可用的所有电信号线，并且可以通过不同的电信号线组向不同组的非易失性存储器件发出数据访问命令。存储器总线可以可用并且被配置用于与存储器控制器和易失性存储器设备或存储控制器和非易失性存储器设备一起使用。

5. 发明授权

US08463948B1 Method, apparatus and system for determining an identifier of a volume of memory 有权
标题翻译：用于确定存储器容积的标识符的方法，装置和系统
公开(公告)号：US08463948B1
公开(公告)日：2013-06-11
申请号：US13175721
申请日：2011-07-01
申请人： Shekoufeh Qawami , Robert W. Faber
发明人： Shekoufeh Qawami , Robert W. Faber
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F3/0611 , G06F3/0632 , G06F3/0679
摘要： Techniques for determining an identifier for a volume of memory in a memory device of a computer system. In an embodiment, the memory device detects an indication of an initialization event of the computer system and receives command information after the detecting of the indication. In certain embodiments, the memory device stores an identifier value for association with the volume of memory, wherein the storing is based on whether the received command information specifies that the volume of memory is to be assigned an identifier.
摘要翻译：用于确定计算机系统的存储器设备中的存储器容量的标识符的技术。在一个实施例中，存储器装置检测计算机系统的初始化事件的指示，并且在检测到指示之后接收命令信息。在某些实施例中，存储器设备存储用于与存储器卷相关联的标识符值，其中存储基于所接收的命令信息是否指定要为存储器卷分配标识符。

6. 发明授权

US08595597B2 Adjustable programming speed for NAND memory devices 有权
标题翻译： NAND存储器件可编程速度可调
公开(公告)号：US08595597B2
公开(公告)日：2013-11-26
申请号：US13039553
申请日：2011-03-03
申请人： Ningde Xie , Matthew Goldman , Jawad B. Khan , Robert W. Faber
发明人： Ningde Xie , Matthew Goldman , Jawad B. Khan , Robert W. Faber
IPC分类号： G11C29/00 , G06F11/00
CPC分类号： G06F11/1048 , G11C16/00 , G11C29/021 , G11C29/028 , G11C29/52 , G11C2029/0409 , G11C2029/0411
摘要： Embodiments of the invention describe methods, systems and apparatuses to improve solid state device (SSD) write speed by efficiently utilizing error correction code executed for the device. SSDs may be comprised of several NAND memory devices. It is understood that such devices tend to have a raw bit error rate (RBER) that is related to the program/erase cycle count for the device.Embodiments of the invention efficiently use system ECC by changing the operating conditions of the SSD to better utilize the robustness of the implemented ECC algorithm. For example, embodiments of the invention may alter the programming voltage supplied to an SSD to increase write speed; such an increase may increase the RBER of the device, but will not affect the accuracy of such operations due to the ECC that is provisioned for end of life storage fidelity (i.e., the RBER that will occur at the end of life).
摘要翻译：本发明的实施例描述了通过有效利用为设备执行的纠错码来改善固态设备（SSD）写入速度的方法，系统和装置。 SSD可以由多个NAND存储器件组成。应当理解，这样的设备倾向于具有与设备的编程/擦除周期计数相关的原始误码率（RBER）。本发明的实施例通过改变SSD的操作条件来有效地使用系统ECC，以更好地利用所实施的ECC算法的鲁棒性。例如，本发明的实施例可以改变提供给SSD的编程电压以增加写入速度; 这样的增加可能增加设备的RBER，但是由于为终端存储保真度（即，将在生命结束时发生的RBER）提供的ECC而不会影响这种操作的准确性。

7. 发明授权

US07516267B2 Recovering from a non-volatile memory failure 有权
标题翻译：从非易失性存储器故障中恢复
公开(公告)号：US07516267B2
公开(公告)日：2009-04-07
申请号：US11266119
申请日：2005-11-03
申请人： Richard L. Coulson , Sanjeev N. Trika , Robert W. Faber
发明人： Richard L. Coulson , Sanjeev N. Trika , Robert W. Faber
IPC分类号： G06F12/16
CPC分类号： G11C16/349 , G06F12/0246
摘要： Write operations store data in different physical memory locations. Each of the physical memory locations are associated with a logical address that is shared in common among the physical addresses. Sequence information stored in the physical memory location indicates which one of the write operations occurred last. The available erased memory location can be split into a list of erased memory locations available to be used and a list of erased memory locations not available to be used. Then, on a failure, only the list of erased memory locations available to be used needs to be analyzed to reconstruct the consumption states of memory locations.
摘要翻译：写操作将数据存储在不同的物理内存位置。每个物理存储器位置与物理地址中共同共享的逻辑地址相关联。存储在物理存储器位置的序列信息指示最后发生哪个写入操作。可用的擦除的存储器位置可以被拆分为可用于被使用的擦除的存储器位置的列表和不可用的擦除的存储器位置的列表。然后，在故障时，仅需要分析可用于被使用的擦除的存储器位置的列表，以重建存储器位置的消耗状态。

8. 发明授权

US07286387B2 Reducing the effect of write disturbs in polymer memories 有权
公开(公告)号：US07286387B2
公开(公告)日：2007-10-23
申请号：US11126685
申请日：2005-05-11
申请人： Richard L. Coulson , Jonathan C. Lueker , Robert W. Faber
发明人： Richard L. Coulson , Jonathan C. Lueker , Robert W. Faber
IPC分类号： G11C11/00
CPC分类号： B82Y10/00 , G11C11/22 , G11C13/0014 , G11C13/0016 , G11C13/0033 , G11C13/0069 , G11C16/3431
摘要： The write disturb that occurs in polymer memories may be reduced by writing back data after a read in a fashion which offsets any effect on the polarity of bits in bit lines associated with the addressed bit. For example, each time the data is written back, its polarity may be alternately changed. In another embodiment, the polarity may be randomly changed.

9. 发明授权

US06801196B1 Method and apparatus to control power state of a display device 有权
标题翻译：控制显示装置的电源状态的方法和装置
公开(公告)号：US06801196B1
公开(公告)日：2004-10-05
申请号：US09442872
申请日：1999-11-18
申请人： Andrew D. Bodley , Robert W. Faber
发明人： Andrew D. Bodley , Robert W. Faber
IPC分类号： G09G510
CPC分类号： G06F1/3265 , G06F1/3203 , G09G2330/022 , Y02D10/153
摘要： A method includes applying a power control signal from a computer system to a display device, and maintaining the display device in a first reduced power consumption state while the power control signal is applied.
摘要翻译：一种方法包括将来自计算机系统的功率控制信号施加到显示装置，并且在施加功率控制信号时将显示装置维持在第一降低功耗状态。

10. 发明授权

US09141536B2 Nonvolatile memory wear management 有权
标题翻译：非易失性内存磨损管理
公开(公告)号：US09141536B2
公开(公告)日：2015-09-22
申请号：US13991392
申请日：2011-11-04
申请人： Robert W. Faber
发明人： Robert W. Faber
IPC分类号： G06F12/00 , G06F12/02 , G11C16/34
CPC分类号： G06F12/0246 , G06F2212/7211 , G11C16/349
摘要： Embodiments describe methods, apparatus, and system configurations for providing targeted wear management in nonvolatile memory. Specifically, embodiments may include a memory controller to receive a memory access request directed to a storage unit of the nonvolatile memory. The memory controller may access metadata in the storage unit and determine whether to perform a memory access in accordance with the memory access request based on the state information. Other embodiments may be described or claimed.
摘要翻译：实施例描述了用于在非易失性存储器中提供目标磨损管理的方法，装置和系统配置。具体地，实施例可以包括存储器控制器，用于接收针对非易失性存储器的存储单元的存储器访问请求。存储器控制器可以访问存储单元中的元数据，并且基于状态信息来确定是否根据存储器访问请求执行存储器访问。可以描述或要求保护其他实施例。

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