专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120205973A1 Pseudo-Random Bit Sequence Generation for Maximum Power Point Tracking in Photovoltaic Arrays 有权
标题翻译：光伏阵列中最大功率点跟踪的伪随机位序列生成
公开(公告)号：US20120205973A1
公开(公告)日：2012-08-16
申请号：US13359695
申请日：2012-01-27
申请人： Shawn R. McCaslin , Bertrand J. Williams
发明人： Shawn R. McCaslin , Bertrand J. Williams
IPC分类号： H02J1/10 , G05F1/46
CPC分类号： H02J3/385 , Y02E10/58 , Y10S323/906 , Y10T307/305 , Y10T307/707
摘要： A converter unit configured to couple to a photovoltaic panel (PV) may include a controller to sense an input voltage and input current obtained from the photovoltaic panel, and manage the output voltage of a corresponding power converter coupled to a DC bus to regulate the resultant bus voltage to a point that reduces overall system losses, and removes non-idealities when the panels are series connected. The controller may also perform input voltage management and regulation, including maximum power point tracking (MPPT) for the PV. The controller may probe the bus voltage using a probe waveform generated according to a pseudo-random bit sequence (PRBS), to provide a probe signal that is distinct from the control steps performed by the controller. A PV array may feature a respective converter unit coupled to each PV, with each respective controller using a different and unique seed for generating its PRBS.
摘要翻译：配置成耦合到光伏面板（PV）的转换器单元可以包括用于感测从光伏面板获得的输入电压和输入电流的控制器，并且管理耦合到DC总线的相应功率转换器的输出电压以调节所得到的总线电压降低整体系统损耗，并且在面板串联连接时消除非理想性。控制器还可以执行输入电压管理和调节，包括PV的最大功率点跟踪（MPPT）。控制器可以使用根据伪随机位序列（PRBS）生成的探针波形来探测总线电压，以提供与由控制器执行的控制步骤不同的探测信号。 PV阵列可以具有耦合到每个PV的相应转换器单元，其中每个相应的控制器使用不同且唯一的种子来产生其PRBS。

2. 发明授权

US08970068B2 Pseudo-random bit sequence generation for maximum power point tracking in photovoltaic arrays 有权
标题翻译：光伏阵列中最大功率点跟踪的伪随机位序列生成
公开(公告)号：US08970068B2
公开(公告)日：2015-03-03
申请号：US13359695
申请日：2012-01-27
申请人： Shawn R. McCaslin , Bertrand J. Williams
发明人： Shawn R. McCaslin , Bertrand J. Williams
IPC分类号： H02J3/00 , H02J3/38
CPC分类号： H02J3/385 , Y02E10/58 , Y10S323/906 , Y10T307/305 , Y10T307/707
摘要： A converter unit configured to couple to a photovoltaic panel (PV) may include a controller to sense an input voltage and input current obtained from the photovoltaic panel, and manage the output voltage of a corresponding power converter coupled to a DC bus to regulate the resultant bus voltage to a point that reduces overall system losses, and removes non-idealities when the panels are series connected. The controller may also perform input voltage management and regulation, including maximum power point tracking (MPPT) for the PV. The controller may probe the bus voltage using a probe waveform generated according to a pseudo-random bit sequence (PRBS), to provide a probe signal that is distinct from the control steps performed by the controller. A PV array may feature a respective converter unit coupled to each PV, with each respective controller using a different and unique seed for generating its PRBS.
摘要翻译：配置成耦合到光伏面板（PV）的转换器单元可以包括用于感测从光伏面板获得的输入电压和输入电流的控制器，并且管理耦合到DC总线的相应功率转换器的输出电压以调节所得到的总线电压降低整体系统损耗，并且在面板串联连接时消除非理想性。控制器还可以执行输入电压管理和调节，包括PV的最大功率点跟踪（MPPT）。控制器可以使用根据伪随机位序列（PRBS）生成的探针波形来探测总线电压，以提供与由控制器执行的控制步骤不同的探测信号。 PV阵列可以具有耦合到每个PV的相应转换器单元，其中每个相应的控制器使用不同且唯一的种子来产生其PRBS。

3. 发明申请

US20120319489A1 Power Shuffling Solar String Equalization System 审中-公开
标题翻译：电力洗牌太阳能线束均衡系统
公开(公告)号：US20120319489A1
公开(公告)日：2012-12-20
申请号：US13492084
申请日：2012-06-08
申请人： Shawn R. McCaslin , Bertrand J. Williams
发明人： Shawn R. McCaslin , Bertrand J. Williams
IPC分类号： H02J1/00
CPC分类号： H02J1/10 , H02H1/0015 , H02H7/20 , H02J1/12 , H02J3/385 , Y02E10/58 , Y10T307/685
摘要： A photovoltaic (PV) array system may include multiple PV strings, each PV string including respective PV panels coupled in series. Each PV string may be coupled in series with a first terminal of a respective string equalizer module. The string equalizer module may equalize a maximum power-point voltage (VMP) of the PV string before the PV strings combine to produce a single, composite DC bus voltage on a DC bus. To accomplish this, each string equalizer module may generate a respective adaptive string equalizer output voltage at its first terminal to tune a respective PV string voltage of its corresponding respective PV string to have the VMP of its corresponding PV string match respective VMP's of other PV strings. That is, PV strings may sink or source power from/to other PV strings, to equalize the VMP of each corresponding respective PV string.
摘要翻译：光伏（PV）阵列系统可以包括多个PV串，每个PV串包括串联耦合的各个PV板。每个PV串可以与相应串均衡器模块的第一端串联耦合。串均衡器模块可以在PV串组合之前均衡PV串的最大功率点电压（VMP），以在DC总线上产生单个复合DC总线电压。为了实现这一点，每个串均衡器模块可以在其第一端产生相应的自适应串均衡器输出电压，以调谐其对应的相应PV串的相应PV串电压，使其相应PV串的VMP与其他PV串的相应VMP相匹配。也就是说，PV串可以从/到其他PV串的电源或源功率来均衡每个对应的相应PV串的VMP。

4. 发明授权

US09106105B2 Regulation of inverter DC input voltage in photovoltaic arrays 有权
标题翻译：光伏阵列中逆变器直流输入电压的调节
公开(公告)号：US09106105B2
公开(公告)日：2015-08-11
申请号：US13362214
申请日：2012-01-31
申请人： Shawn R. McCaslin , Sam B. Sandbote , Bertrand J. Williams
发明人： Shawn R. McCaslin , Sam B. Sandbote , Bertrand J. Williams
IPC分类号： H02J3/38
CPC分类号： H02J3/385 , Y02E10/58 , Y10S323/906 , Y10T307/305 , Y10T307/707
摘要： A converter unit configured to couple to a photovoltaic panel (PV) may include a controller to sense an output voltage and output current produced by the photovoltaic panel, and manage the output voltage of a corresponding power converter coupled to a DC bus to regulate the resultant bus voltage to a point that reduces overall system losses, and removes non-idealities when the panels are series connected. The controller may also adapt to output condition constraints, and perform a combination of input voltage and output voltage management and regulation, including maximum power point tracking (MPPT) for the PV. The output voltage and output current characteristic of the power converter may be shaped to present a power gradient—which may be hysteretically controlled—to the DC bus to compel an inverter coupled to the DC bus to perform its own MPPT to hold the DC-bus voltage within a determinate desired operating range.
摘要翻译：配置成耦合到光伏面板（PV）的转换器单元可以包括用于感测由光伏面板产生的输出电压和输出电流的控制器，并且管理耦合到DC总线的相应功率转换器的输出电压以调节所得到的总线电压降低整体系统损耗，并且在面板串联连接时消除非理想性。控制器还可以适应输出条件约束，并且执行输入电压和输出电压管理和调节的组合，包括PV的最大功率点跟踪（MPPT）。功率转换器的输出电压和输出电流特性可以被成形为呈现对于DC总线的功率梯度（其可能被迟滞地控制），以迫使耦合到DC总线的逆变器执行其自身的MPPT来保持DC总线电压在确定的期望工作范围内。

5. 发明申请

US20120205974A1 Regulation of Inverter DC Input Voltage in Photovoltaic Arrays 有权
标题翻译：光伏阵列逆变器直流输入电压的调节
公开(公告)号：US20120205974A1
公开(公告)日：2012-08-16
申请号：US13362214
申请日：2012-01-31
申请人： Shawn R. McCaslin , Sam B. Sandbote , Bertrand J. Williams
发明人： Shawn R. McCaslin , Sam B. Sandbote , Bertrand J. Williams
IPC分类号： H02J1/10 , H02M7/44 , G05F1/46
CPC分类号： H02J3/385 , Y02E10/58 , Y10S323/906 , Y10T307/305 , Y10T307/707
摘要： A converter unit configured to couple to a photovoltaic panel (PV) may include a controller to sense an output voltage and output current produced by the photovoltaic panel, and manage the output voltage of a corresponding power converter coupled to a DC bus to regulate the resultant bus voltage to a point that reduces overall system losses, and removes non-idealities when the panels are series connected. The controller may also adapt to output condition constraints, and perform a combination of input voltage and output voltage management and regulation, including maximum power point tracking (MPPT) for the PV. The output voltage and output current characteristic of the power converter may be shaped to present a power gradient—which may be hysteretically controlled—to the DC bus to compel an inverter coupled to the DC bus to perform its own MPPT to hold the DC-bus voltage within a determinate desired operating range.
摘要翻译：配置成耦合到光伏面板（PV）的转换器单元可以包括用于感测由光伏面板产生的输出电压和输出电流的控制器，并且管理耦合到DC总线的相应功率转换器的输出电压以调节所得到的总线电压降低整体系统损耗，并且在面板串联连接时消除非理想性。控制器还可以适应输出条件约束，并且执行输入电压和输出电压管理和调节的组合，包括PV的最大功率点跟踪（MPPT）。功率转换器的输出电压和输出电流特性可以被成形为呈现对于DC总线的功率梯度（其可能被迟滞地控制），以迫使耦合到DC总线的逆变器执行其自身的MPPT来保持DC总线电压在确定的期望工作范围内。

6. 发明授权

US4989169A Digital tone detector using a ratio of two demodulators of differing frequency 失效
标题翻译：数字音调检测器使用两个不同频率的解调器的比例
公开(公告)号：US4989169A
公开(公告)日：1991-01-29
申请号：US474607
申请日：1990-02-05
申请人： Shawn R. McCaslin , Tim A. Williams , Nicholas R. van Bavel
发明人： Shawn R. McCaslin , Tim A. Williams , Nicholas R. van Bavel
IPC分类号： H03D3/00
CPC分类号： H03D3/007 , H03D2200/0056
摘要： A digital tone detector receives a modulated input signal selectively containing at least one tone signal component. Two demodulator circuits each demodulate the input signal wherein one demodulator circuit operates at the predetermined frequency of the tone and the other demodulator circuit operates at the second harmonic. When the input tone has a low spectral harmonic power, a ratio of the demodulated outputs of the two demodulators reliably detects the presence of the tone in the input signal.
摘要翻译：数字音调检测器接收选择性地包含至少一个音调信号分量的调制输入信号。两个解调器电路各自解调输入信号，其中一个解调器电路以音调的预定频率工作，另一个解调器电路以二次谐波工作。当输入音具有低频谱谐波功率时，两个解调器的解调输出的比率可靠地检测输入信号中的音调的存在。

7. 发明授权

US5631900A Double-Talk detector for echo canceller 失效
标题翻译：用于回波消除器的双向探测器
公开(公告)号：US5631900A
公开(公告)日：1997-05-20
申请号：US536986
申请日：1995-09-29
申请人： Shawn R. McCaslin , Nariankadu D. Hemkumar , Bheeshmar Redheendran
发明人： Shawn R. McCaslin , Nariankadu D. Hemkumar , Bheeshmar Redheendran
IPC分类号： H04B3/23
CPC分类号： H04B3/234
摘要： A double-talk detector for an echo canceller includes power estimators (60) and (62) which are utilized to measure the ERLE value in a calculator (64). This ERLE value is stored in a register (70) when it is the largest value generated. This register (70) is updated whenever a new and better ERLE occurs. A fraction of the value in register (70) is utilized as an input to a comparator (88), and then compared to the current ERLE value. If the current ERLE differs from the SERLE in register (70) an inhibit signal is generated for blocking the updates of an adaptive filter (40). The value stored in the register (70) is periodically decremented to reduce the value thereof. This decrement operation is performed in response to detection of an utterance from the far-end.
摘要翻译：用于回波消除器的双方通话检测器包括用于在计算器（64）中测量ERLE值的功率估计器（60）和（62）。当它是生成的最大值时，该ERLE值存储在寄存器（70）中。每当发生新的和更好的ERLE时，该寄存器（70）被更新。将寄存器（70）中的值的一小部分用作比较器（88）的输入，然后与当前的ERLE值进行比较。如果当前的ERLE与寄存器（70）中的SERLE不同，则产生阻止自适应滤波器（40）的更新的禁止信号。存储在寄存器（70）中的值被周期性地递减，以减小它的值。响应于从远端发出的话语的检测来执行该递减操作。

8. 发明授权

US06876699B1 Filter circuit for a bit pump and method of configuring the same 有权
标题翻译：一种位泵的滤波电路及其配置方法
公开(公告)号：US06876699B1
公开(公告)日：2005-04-05
申请号：US09650851
申请日：2000-08-29
申请人： Mandeep Singh Chadha , Zhuo Fu , Shawn R. McCaslin , Nicholas R. van Bavel
发明人： Mandeep Singh Chadha , Zhuo Fu , Shawn R. McCaslin , Nicholas R. van Bavel
IPC分类号： H03H7/30 , H04L25/03
CPC分类号： H04L25/03057 , H04L2025/03503
摘要： A filter circuit, method of configuring the filter circuit, and a bit pump and transceiver employing the circuit and method. In one embodiment, the filter circuit includes a noise prediction equalizer that generates a noise prediction equalizer coefficient during activation of the bit pump to reduce an intersymbol interference associated with a receive signal propagating along a receive path of the bit pump. The filter circuit also includes a decision feedback equalizer that generates a decision feedback equalizer coefficient during the activation of the bit pump to reduce the intersymbol interference associated with the receive signal. The noise prediction equalizer is concatenated with the decision feedback equalizer during showtime of the bit pump to form a precoder associated with a transmit path of the bit pump.
摘要翻译：滤波电路，滤波器电路的配置方法以及采用该电路和方法的位泵和收发器。在一个实施例中，滤波器电路包括噪声预测均衡器，其在位泵的激活期间产生噪声预测均衡器系数，以减少与沿着位泵的接收路径传播的接收信号相关联的符号间干扰。滤波器电路还包括判决反馈均衡器，其在比特泵的激活期间产生判决反馈均衡器系数，以减少与接收信号相关联的符号间干扰。在比特泵的显示时间期间，噪声预测均衡器与判决反馈均衡器连接以形成与比特泵的发送路径相关联的预编码器。

9. 发明授权

US5864793A Persistence and dynamic threshold based intermittent signal detector 失效
标题翻译：基于持续性和动态阈值的间歇信号检测器
公开(公告)号：US5864793A
公开(公告)日：1999-01-26
申请号：US693374
申请日：1996-08-06
申请人： Hakim M. Mesiwala , Shawn R. McCaslin
发明人： Hakim M. Mesiwala , Shawn R. McCaslin
IPC分类号： G10L11/02 , G10L3/02
CPC分类号： G10L25/78 , G10L2025/783
摘要： A signal detector for detecting the presence of a intermittent signal component in a signal. The signal detector receives each of the signal strength samples during a corresponding iteration, and compares a threshold value with the received signal sample. The signal detector sets a counter to a pre-determined number if the sample compared is greater than the threshold value. The signal detector decrements the persistence counter if a corresponding sample is not greater than the threshold value. If the persistence counter is greater than a trigger value, the detector indicates the presence of a intermittent signal component or otherwise declares the absence of a intermittent signal component. The detector may indicate the presence of a intermittent signal component by a logical value of 1 and the absence by a logical value of 0. The threshold value is composed of two components; the intermittent signal component and the background signal component. Each of the components of the threshold is determined separately by using a tracker and a low pass estimator under a control signal obtained from previous decisions as to whether intermittent signal was present or absent.
摘要翻译：一种用于检测信号中间歇信号分量的存在的信号检测器。信号检测器在相应的迭代期间接收每个信号强度样本，并将阈值与接收到的信号样本进行比较。如果所比较的样本大于阈值，则信号检测器将计数器设置为预定数。如果对应的样本不大于阈值，则信号检测器将持续计数器递减。如果持续计数器大于触发值，则检测器指示存在间歇信号分量，否则声明不存在间歇信号分量。检测器可以通过逻辑值1指示间歇信号分量的存在，并且不存在逻辑值0。阈值由两个分量组成; 间歇信号分量和背景信号分量。通过使用跟踪器和低通估计器来分别确定阈值的每个分量，所述跟踪器和低通估计器根据先前关于间歇信号是否存在的决定获得的控制信号。

10. 发明授权

US5036294A Phase locked loop having low-frequency jitter compensation 失效
标题翻译：锁相环具有低频抖动补偿
公开(公告)号：US5036294A
公开(公告)日：1991-07-30
申请号：US620686
申请日：1990-12-03
申请人： Shawn R. McCaslin
发明人： Shawn R. McCaslin
IPC分类号： H03L7/06 , H03L7/093 , H03L7/099 , H03L7/18
CPC分类号： H03L7/0991 , H03L7/093 , H03J2200/10
摘要： A phase locked loop circuit generates an output clock that is in phase with a reference clock and is frequency jitter compensated at lower frequencies by translating intrinsic jitter frequency from low frequency to a predetermined range of higher frequencies. The phase locked loop circuit utilizes dithering circuitry to control a switched capacitor network in order to reduce the magnitude of the frequency jitter at lower frequencies. A phase detector and a loop filter of the phase locked loop circuit are implemented using digital circuitry. An oscillator of the phase locked loop is an analog oscillator which is digitally controlled and includes the switched capacitor network. Quantization error in the output clock is minimized by switching an LSB weighted capacitor in the oscillator at a frequency established by the dithering circuitry.
摘要翻译：锁相环电路产生与参考时钟同相的输出时钟，并且通过将本征抖动频率从低频转换到较高频率的预定范围，并且在较低频率处进行频率抖动补偿。锁相环电路利用抖动电路来控制开关电容器网络，以便在较低频率下降低频率抖动的幅度。使用数字电路实现锁相环电路的相位检测器和环路滤波器。锁相环的振荡器是数字控制的模拟振荡器，包括开关电容网络。通过以抖动电路建立的频率切换振荡器中的LSB加权电容，使输出时钟的量化误差最小化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式