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1. 发明专利

JP2015002330A 窒化物半導体装置审中-公开
标题翻译：氮化物半导体器件
公开(公告)号：JP2015002330A
公开(公告)日：2015-01-05
申请号：JP2013127676
申请日：2013-06-18
申请人：シャープ株式会社 , Sharp Corp
发明人： ANDO TAKAHIKO , TERAGUCHI NOBUAKI , SATO SHINICHI
IPC分类号： H01L21/338 , H01L29/417 , H01L29/778 , H01L29/812
摘要：【課題】短手方向に並んだ複数のドレイン電極のうちの端のドレイン電極に接続するビアホールの破壊の発生を軽減した窒化物半導体装置を提供すること。【解決手段】短手方向に並んだ上記複数のドレイン電極11のうち、上記短手方向の最も外側のドレイン電極11は、ビアホール45を介して、ソース電極パッド32に接続されている。一方、上記短手方向に並んだ上記複数のドレイン電極11のうち、上記短手方向の最も外側のドレイン電極以外のドレイン電極11は、ビアホール25を介して、上記ドレイン電極パッド31に接続されている。複数のソース電極12は、ビアホール26を介して、ソース電極パッド32に接続されている。【選択図】図2
摘要翻译：要解决的问题：提供一种氮化物半导体器件，其中在横向方向上布置的多个漏极中的端部处的与漏电极连接的通孔的破坏发生减少。解决方案：最外层漏极在横向上排列的多个漏电极11中的电极11经由通孔45与源极电极焊盘32连接。除了最外侧漏极以外的漏电极在横方向外沿横向布置的多个漏电极11经由通孔25与漏电极焊盘31连接。多个源电极12经由通孔26与源电极焊盘32连接。

2. 发明专利

JP2013030647A High voltage test method 审中-公开
标题翻译：高电压测试方法
公开(公告)号：JP2013030647A
公开(公告)日：2013-02-07
申请号：JP2011166346
申请日：2011-07-29
申请人： Sharp Corp , シャープ株式会社
发明人： FURUKABU TOSHIAKI , SATO SHINICHI
IPC分类号： H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide a high voltage test method capable of preventing air discharge in the high voltage test of a wafer with simple configuration.SOLUTION: In the resist patterning process following to the electrode pad formation process, a resist pattern 6 is formed so as to cover a gap region between a source electrode pad 3 and a drain electrode pad 4 adjacent to each other and the fringe region of the source electrode pad 3 and drain electrode pad 4 near the gap region, and so that the shortest distance of the exposed part 3a of the source electrode pad 3 and the exposed part 4a of the drain electrode pad 4 adjacent to each other is longer than a preset inter-electrode distance.
摘要翻译：要解决的问题：提供一种能够以简单的结构在晶片的高压测试中防止空气放电的高压测试方法。解决方案：在电极焊盘形成工艺之后的抗蚀剂图案化工艺中，形成抗蚀剂图案6，以覆盖彼此相邻的源极电极焊盘3和漏电极焊盘4之间的间隙区域和边缘源极电极焊盘3和漏极电极焊盘4的接近间隙区域，并且使得源极电极焊盘3的露出部分3a和漏电极焊盘4的暴露部分4a彼此相邻的最短距离为比预设的电极间距离长。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2012238808A Field-effect transistor 审中-公开
标题翻译：场效应晶体管
公开(公告)号：JP2012238808A
公开(公告)日：2012-12-06
申请号：JP2011108463
申请日：2011-05-13
申请人： Sharp Corp , シャープ株式会社
发明人： TODA SHINICHI , NAGAHISA TETSUZO , SATO SHINICHI
IPC分类号： H01L21/338 , H01L29/41 , H01L29/417 , H01L29/778 , H01L29/812
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/402 , H01L29/41758
摘要： PROBLEM TO BE SOLVED: To provide a GaN based HFET capable of minimizing reduction of dynamic breakdown voltage.SOLUTION: In the GaN based HFET, a length L2 of each source electrode 12 in the longitudinal direction is equal to a length L1 of each drain electrode 11 in the longitudinal direction. Positions in the longitudinal direction of longitudinal ends 12A and 12B of the source electrode 12 match the positions in the longitudinal direction of longitudinal ends 11A and 11B of the drain electrode 11. Concentration of the electron flow from the ends 12A and 12B of the source electrode 12 toward the ends 11A and 11B of the drain electrode 11 can be avoided by a configuration where the both longitudinal ends 12A and 12B of the source electrode 12 do not project farther outward than the both longitudinal ends 11A and 11B of the drain electrode 11 in the longitudinal direction.
摘要翻译：要解决的问题：提供能够最小化动态击穿电压降低的GaN基HFET。解决方案：在GaN基HFET中，每个源电极12的纵向长度L2等于每个漏电极11在纵向方向上的长度L1。源电极12的纵向端部12A和12B的纵向方向上的位置与漏电极11的纵向端部11A和11B的纵向方向上的位置相匹配。源电极的端部12A和12B的电子流的浓度可以通过源电极12的两个纵向端部12A和12B不比漏电极11的两个纵向端部11A和11B向外突出的构造来避免漏极电极11的端部11A和11B，纵向。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2008243263A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2008243263A
公开(公告)日：2008-10-09
申请号：JP2007079991
申请日：2007-03-26
申请人： Sharp Corp , シャープ株式会社
发明人： ISHIHARA KAZUYA , AWAYA NOBUYOSHI , HOSOI YASUNARI , SATO SHINICHI , HORII SHINJI
IPC分类号： G11C13/00
CPC分类号： G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/31
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device for surely rewriting data in a memory cell array including a variable resistance element at high speed and with low electric power. SOLUTION: The semiconductor memory device has a memory cell array 30 having memory cells 20 arrayed in a matrix shape, the memory cell 20 being composed of: a variable resistance element 21 having an electric resistance shifting from a first state to a second state when a first rewriting voltage is applied to the element and from the second state to the first state when a second rewriting voltage is applied to the element; and a selection transistor 22 with a source or a drain connected to the one end of the variable resistance element 21. The semiconductor memory device also has a means for sequentially executing the following processing: initializing processing for sequentially selecting a first predetermined number or less of memory cells among all the memory cells, and sequentially executing the rewriting operation based on the application of the first rewriting voltage to set all electric resistances to the second state; and individual rewriting processing for sequentially selecting, a second predetermined number or less of memory cells among some memory cells whose electric resistances are set to the first state, and sequentially executing a rewriting operation based on application of the second rewriting voltage. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于在包括可变电阻元件的存储单元阵列中以高速和低功率可靠地重写数据的半导体存储器件。解决方案：半导体存储器件具有存储单元阵列30，存储单元阵列30以矩阵形式排列，存储单元20由以下部分组成：可变电阻元件21，其电阻从第一状态转变到第二状态当向元件施加第二重写电压时，向元件施加第一重写电压并从第二状态施加到第一状态的状态; 以及选择晶体管22，其源极或漏极连接到可变电阻元件21的一端。半导体存储器件还具有用于顺序执行以下处理的装置：用于顺序地选择第一预定数量或更小的初始化处理的初始化处理存储器单元，并且基于施加第一重写电压来顺序地执行重写操作，以将所有电阻设置为第二状态; 以及单独重写处理，用于在电阻被设置为第一状态的一些存储单元中顺序地选择第二预定数量或更少的存储单元，并且基于施加第二重写电压来顺序地执行重写操作。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2008108848A Semiconductor memory device and its manufacturing method 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2008108848A
公开(公告)日：2008-05-08
申请号：JP2006289096
申请日：2006-10-24
申请人： Sharp Corp , シャープ株式会社
发明人： NAKANO MASAYUKI , IWATA HIROSHI , SATO SHINICHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of reducing a fluctuation in initial characteristics, deterioration in endurance and a characteristic variation, and its manufacturing method. SOLUTION: A gate length of a gate electrode 108 gradually gets longer as it comes farther away from a gate oxide film 107. A charge retention film 103 is formed with an approximately uniform thickness on a semiconductor substrate 101 via a tunnel oxide film 102, so that there is no place to which electrons accumulated in the charge retention film 103 move and the fluctuation in characteristics can be inhibited. In addition, a quantity of recombination between an electron and a hole can be suppressed, thereby inhibiting the deterioration in endurance. The tunnel oxide film 102 is formed with an approximately uniform thickness. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供能够减少初始特性的波动，耐久性和特性变化的半导体存储器件及其制造方法。解决方案：栅电极108的栅极长度越远离栅极氧化膜107越来越长。电荷保持膜103通过隧道氧化膜在半导体衬底101上形成具有大致均匀厚度的电荷保持膜103 102，使得电荷积聚在电荷保持膜103中的电子没有位置移动，并且可以抑制特性的波动。此外，可以抑制电子和空穴之间的复合量，从而抑制耐久性的劣化。隧道氧化膜102形成为具有大致均匀的厚度。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2005244167A Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：JP2005244167A
公开(公告)日：2005-09-08
申请号：JP2004298865
申请日：2004-10-13
申请人： Sharp Corp , シャープ株式会社
发明人： HIROHAMA KAZUHIRO , TANAKA MASARU , HASHIMOTO HISAYOSHI , SATO SHINICHI , KANZAWA HIDEYUKI
IPC分类号： H01L21/3065 , H01L21/76 , H01L21/762 , H01L21/8234
CPC分类号： H01L21/76232 , H01L21/823481
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which can process silicone nitride film vertically at a pattern interval narrower than the limit resolution width of a photolithography technology in patterning the silicone nitride film used as a mask of trench etching at the time of shallow isolation formation. SOLUTION: The manufacturing method of the semiconductor device comprises steps of: forming a silicone oxide film, the silicone nitride film, and a silicon nitride oxide film in order on a silicone substrate; forming a resist pattern having an opening at a location corresponding to an element isolation region of the silicone substrate; forming a trench having a pair of taper side surfaces which incline in a direction where they approach mutually toward substrate side at a counter side surface using the resist pattern as the mask; and patterning the silicone nitride film and the silicone oxide film by dry etching using the resist pattern and the silicon nitride oxide film as masks. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体器件的制造方法，该半导体器件可以以比用于作为沟槽掩模的硅氮化物膜图案化的光刻技术的极限分辨率宽度更窄的图案间隔垂直处理硅氮化物膜在浅隔离形成时进行蚀刻。解决方案：半导体器件的制造方法包括以下步骤：在有机硅衬底上依次形成氧化硅膜，氮化硅膜和氮氧化硅膜; 在对应于所述硅树脂基板的元件隔离区域的位置处形成具有开口的抗蚀剂图案; 形成沟槽，其具有一对锥形侧表面，所述一对锥形侧表面使用所述抗蚀剂图案作为所述掩模，在相对侧面朝向基板侧相互接近的方向上倾斜; 并通过使用抗蚀剂图案和氮氧化硅膜作为掩模的干蚀刻图案化氮化硅膜和氧化硅膜。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2012244185A Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：JP2012244185A
公开(公告)日：2012-12-10
申请号：JP2012174113
申请日：2012-08-06
申请人： Sharp Corp , シャープ株式会社
发明人： TODA SHINICHI , NAGAHISA TETSUZO , SATO SHINICHI
IPC分类号： H01L21/338 , H01L29/41 , H01L29/417 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a GaN based HFET which can restrict reduction in dynamic withstand voltage.SOLUTION: In a GaN based HFET, a two-dimensional electron gas removal region 260B is located outward in the longer direction with respect to a virtual line M71 extending in the short direction from one end part 211A of the longer direction of a drain electrode 211, and is formed in a GaN based laminate 205 beneath a region adjacent in the short direction to one end part 212A of a source electrode 212. Also, a two-dimensional electron gas removal region 260A abuts on the outer side in the longer direction of the two-dimensional electron gas removal region 260B, and extends in the short direction along a source electrode connection part 214 from the end part 212A of the source electrode 212. The presence of the two-dimensional electron gas removal regions 260A and 260B prevent the concentration of electron flows heading from the end part 212A of the source electrode 212 toward the end part 211A of the drain electrode 211 due to dynamic fluctuations in electric field at switching time.
摘要翻译：要解决的问题：提供可以限制动态耐受电压降低的GaN基HFET。解决方案：在GaN基HFET中，二维电子气体去除区260B相对于从短方向延伸的虚拟线M71向长方向外侧延伸，漏电极211，并且形成在GaN基层压体205的与短方向相邻的区域的一个端部212A的源极电极212的下方。另外，二维电子束除去区域260A在外侧二维电子
除去区域260B的长方向，沿着源极电极连接部214沿着源极电极212的端部212A沿短路方向延伸。二维电子
除去区域260A和 260B由于切换时间的电场的动态变化，防止从源电极212的端部212A朝向漏电极211的端部211A的电子流的集中。版权所有（C）2013，JPO＆INPIT

8. 发明专利

JP2012238809A Field-effect transistor 审中-公开
标题翻译：场效应晶体管
公开(公告)号：JP2012238809A
公开(公告)日：2012-12-06
申请号：JP2011108466
申请日：2011-05-13
申请人： Sharp Corp , シャープ株式会社
发明人： TODA SHINICHI , NAGAHISA TETSUZO , SATO SHINICHI
IPC分类号： H01L21/338 , H01L29/423 , H01L29/778 , H01L29/812
CPC分类号： H01L29/7787 , H01L29/0657 , H01L29/2003 , H01L29/205 , H01L29/41758 , H01L29/41766 , H01L29/42316 , H01L29/42372 , H01L29/7786
摘要： PROBLEM TO BE SOLVED: To provide a GaN based HFET capable of minimizing reduction of dynamic breakdown voltage.SOLUTION: In the GaN based HFET, a two-dimensional gas removal region 31 where two-dimensional electron gas does not exist is formed in a GaN based laminate 5 under a region adjoining a source electrode 11 and located longitudinally outward of virtual lines M1 and M2 extending in the transverse direction orthogonal to the longitudinal direction from ends 12A and 12B of a drain electrode 12 in the longitudinal direction, and in a GaN based laminate 5 under a region adjoining the longitudinal ends 12A and 12B of a drain electrode 12 on the longitudinal outside. Since the two-dimensional gas removal region 31 exists, concentration of an electron flow from the end of the source electrode 11 toward the end of the drain electrode 12 due to dynamic electric field variation can be avoided at the time of switching.
摘要翻译：要解决的问题：提供能够最小化动态击穿电压降低的GaN基HFET。解决方案：在基于GaN的HFET中，在GaN基层压体5中形成二维气体除去区域31，其中不存在二维电子气体，在邻近源电极11的区域形成并位于虚拟的纵向外侧沿纵向方向从漏电极12的端部12A和12B沿垂直于纵向方向的横向方向延伸的线M1和M2，以及与漏电极的纵向端部12A和12B邻接的区域中的GaN基层压体5 12在纵向外面。由于存在二维气体去除区域31，所以在切换时可以避免由于动态电场变化而从源电极11的端部到漏电极12的端部的电子流的集中。版权所有（C）2013，JPO＆INPIT

9. 发明专利

JP2008052781A Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：JP2008052781A
公开(公告)日：2008-03-06
申请号：JP2006225811
申请日：2006-08-22
申请人： Sharp Corp , シャープ株式会社
发明人： YOSHIMURA SATOSHI , SATO SHINICHI , YAMAGATA SATORU , HORII SHINJI
IPC分类号： G11C13/00 , H01L27/10
CPC分类号： G11C11/22 , G11C13/0007 , G11C13/0069 , G11C17/165 , G11C2013/009 , G11C2213/31 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/147
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory which can impress at least one of the polarities of a voltage across the variable resistor element without the voltage drop by eliminating the effect of the voltage drop equal to the threshold voltage when impressing a positive voltage from the source line side to the memory cell having a variable resistor element and selection transistor. SOLUTION: The voltage supply means 4-6 have both an N channel MOSFET7 and a P channel MOSFET8 driving the source line, in order to change the electric resistance from the first state to the second state, by applying the first rewriting voltage across the variable resistor element 2 by applying the first voltage between the bit line BL and the source line SL and the third voltage to the word line WL connected to the selected memory cell, and also in order to change the electric resistance from the second state to the first state by applying the second rewriting voltage of a polarity opposite to and different in the absolute value from the first rewriting voltage across the variable resistor element by applying the second voltage of a polarity opposite to the first voltage between the bit line and the source line, and the third voltage to the word line. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体存储器，其可以通过消除等于阈值电压时的电压降的影响而在不会产生电压降的情况下施加电压两端的至少一个极性的电压从源极侧到具有可变电阻元件和选择晶体管的存储单元的正电压。解决方案：电压供给装置4-6具有驱动源极线的N沟道MOSFET7和P沟道MOSFET8，以便通过施加第一重写电压来将电阻从第一状态改变到第二状态通过将位线BL和源极线SL之间的第一电压和第三电压施加到连接到所选择的存储单元的字线WL，并且为了从第二状态改变电阻，跨越可变电阻元件2 通过施加与所述位线和所述可变电阻元件之间的所述第一电压相反的极性的极性的所述第二电压，施加与所述可变电阻器元件的所述第一重写电压相反并且与所述绝对值不同的极性的所述第二重写电压，源极线，第三个电压到字线。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2007081106A Nonvolatile semiconductor memory device and its manufacturing method 审中-公开
标题翻译：非线性半导体存储器件及其制造方法
公开(公告)号：JP2007081106A
公开(公告)日：2007-03-29
申请号：JP2005266730
申请日：2005-09-14
申请人： Sharp Corp , シャープ株式会社
发明人： OGATA NOBUHITO , SATO SHINICHI , SAITO MASAHIRO
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To reduce the surface area of a nonvolatile memory cell by suppressing characteristic variations caused by misalignment in the memory cell having a charge accumulator located at a side wall of a gate electrode.
SOLUTION: A memory cell comprises a gate insulating film 5 formed on a semiconductor substrate 2, a gate electrode 6 formed on the gate insulating film 5, charge accumulators 7 formed at both side walls of the gate electrodes 6 in a row direction, a channel region 3 positioned below the gate electrode 6 and the charge accumulator 7, and two diffusion layer regions 4 as diffusion layers buried in the both side surfaces of the semiconductor substrate 2 in a row direction of the channel regions 3. The gate electrodes 6 of two memory cells adjacent in the row direction form gate electrode wiring lines 6a which are passed above the two diffusion layer regions 4 and the two charge accumulators 7 interconnected each other, and extended in the row direction. The two diffusion layer regions 4 are positioned under the gate electrode wiring lines 6a, and the diffusion layer regions 4 of two memory cells adjacent in a column direction are interconnected to form buried diffusion wiring lines 4a extended in the columnar direction.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：通过抑制由位于栅电极的侧壁处的电荷蓄积体的存储单元中的不对准引起的特性变化来减小非易失性存储单元的表面积。解决方案：存储单元包括形成在半导体衬底2上的栅极绝缘膜5，形成在栅极绝缘膜5上的栅电极6，形成在栅电极6的两个侧壁上的电荷累积器7沿行方向位于栅电极6和电荷累积器7下方的沟道区域3和作为扩散层的两个扩散层区域4，这些扩散层区域埋设在沟道区域3的行方向上的半导体衬底2的两个侧表面中。栅电极在行方向上相邻的两个存储单元中的6个形成通过两个扩散层区域4和两个电荷累积器7上方并沿行方向延伸的栅电极布线6a。两个扩散层区域4位于栅电极布线6a的下方，并且在列方向上相邻的两个存储单元的扩散层区域4互连，形成在柱状方向上延伸的掩埋扩散布线4a。版权所有（C）2007，JPO＆INPIT

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