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1. 发明专利

JP2008310894A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2008310894A
公开(公告)日：2008-12-25
申请号：JP2007158472
申请日：2007-06-15
申请人： Sharp Corp , シャープ株式会社
发明人： MIYAMOTO HIROO , MURAKAMI YUKICHI
IPC分类号： G11C11/4072 , G11C11/403 , G11C14/00 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device which can reduce a processing time and a CPU load with a simple configuration for setting configuration information necessary for a normal operation of a non-volatile memory in starting up the power supply. SOLUTION: The semiconductor storage device includes: a volatile semiconductor storage device 20 having a volatile mode register for storing configuration information necessary for executing the normal operation to a first volatile storage area 21; and a non-volatile semiconductor memory 10 having a second non-volatile data storage area 12 and a non-volatile configuration information storage area for storing the configuration information. The non-volatile semiconductor storage device 10 includes: a means 30 for detecting a start-up of the power supply; and a means 13 for automatically transmitting the configuration information to the volatile semiconductor device 20 before the normal operation when the power supply is started up. While the volatile semiconductor device 20 includes a means for receiving the configuration information from the non-volatile semiconductor device 10 to store it in the mode register before executing the normal operation after the power supply is started up. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以通过简单的配置来减少处理时间和CPU负载的半导体存储装置，用于在启动电源时设置用于非易失性存储器的正常操作所需的配置信息。解决方案：半导体存储装置包括：具有用于将执行正常操作所需的配置信息存储到第一易失性存储区域21的易失性模式寄存器的易失性半导体存储装置20; 以及具有用于存储配置信息的第二非易失性数据存储区域12和非易失性配置信息存储区域的非易失性半导体存储器10。非易失性半导体存储装置10包括：用于检测电源启动的装置30; 以及用于在电源启动之前在正常操作之前自动地将配置信息发送到易失性半导体器件20的装置13。虽然易失性半导体器件20包括用于从非易失性半导体器件10接收配置信息以在电源启动之前执行正常操作之前将其存储在模式寄存器中的装置。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2006012351A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2006012351A
公开(公告)日：2006-01-12
申请号：JP2004191161
申请日：2004-06-29
申请人： Sharp Corp , シャープ株式会社
发明人： MIYAMOTO HIROO
IPC分类号： G11C11/401 , G11C11/407
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device which avoids the occurrence of a WAIT signal during reading when consecutively reading data from a plurality of continuous addresses and has small area penalty by suppressing redundant memory cell area.
SOLUTION: The number of memory cells provided in each address of a first address group corresponding to a partial address space of an address space is twice as large as the number of memory cells provided in each address of a second address group corresponding to the address space excepting the first address group. Memory cells of one half of memory cells provided in each address of the first address group and memory cells provided in each address of the second address group are configured so as to be accessible independently of one another. Data are so written that data stored in memory cells of one half of memory cells provided in each address of the first address group, and data stored in memory cells of the other half are identical.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体存储装置，其在从多个连续地址连续读取数据时避免了在读取期间发生WAIT信号，并且通过抑制冗余存储器单元面积而具有小的面积损失。解决方案：与地址空间的部分地址空间相对应的第一地址组的每个地址中提供的存储单元的数量是与在第二地址组对应的第二地址组的每个地址中提供的存储单元数量的两倍地址空间除第一个地址组外。提供在第一地址组的每个地址中的存储器单元的一半的存储单元和在第二地址组的每个地址中提供的存储单元被配置为可以彼此独立地访问。数据被写入，使得存储在提供在第一地址组的每个地址中的一半存储单元的存储单元中的数据和存储在另一半存储单元中的数据是相同的。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2003007054A Semiconductor memory 审中-公开
标题翻译：半导体存储器
公开(公告)号：JP2003007054A
公开(公告)日：2003-01-10
申请号：JP2001182452
申请日：2001-06-15
申请人： Sharp Corp , シャープ株式会社
发明人： MIYAMOTO HIROO , TAKADA SHIGEKAZU
IPC分类号： G11C7/00 , G11C11/403 , G11C11/406 , G11C11/4078
CPC分类号： G11C11/406 , G11C11/4078
摘要： PROBLEM TO BE SOLVED: To reduce output frequency of time-out signals for prohibiting memory access and performing refresh-operation and to reduce current consumption without increasing circuit scale.
SOLUTION: This device has not many refresh-timers for each divided memory banks 2A-2D, but has only one refresh-timer 3, instead of that, as the device has only storage circuits 5A-5D storing whether refreshing is performed or not for each memory banks 2A-2D and refresh address and normal access (read/ write operation by a control signal from the outside) address adjusting circuits 6A-6D, even if a memory block 2 is divided into many memory banks 2A-2D being more than conventional one, increasing largely circuit scale by many refresh-timers as conventional one and making it complex and large scale are prevented.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了减少用于禁止存储器访问和执行刷新操作的超时信号的输出频率，并且在不增加电路规模的情况下降低电流消耗。解决方案：该设备对于每个划分的存储体2A-2D没有多少刷新定时器，但是仅具有一个刷新定时器3，而不是由于器件仅具有存储是否执行刷新的存储电路5A-5D的存储电路每个存储体2A-2D和刷新地址和正常访问（来自外部的控制信号的读/写操作）地址调整电路6A-6D，即使存储块2被划分成多个存储体2A-2D大于常规的，通过许多刷新定时器大大地增加电路规模，并且使其复杂并且防止大规模化。

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