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1. 发明授权

US06470493B1 Computer method and apparatus for safe instrumentation of reverse executable program modules 失效
标题翻译：用于安全检测反向可执行程序模块的计算机方法和装置
公开(公告)号：US06470493B1
公开(公告)日：2002-10-22
申请号：US09410388
申请日：1999-09-30
申请人： Sharon Lea Smith , David Paul Hunter , Robert Cohn , David W. Goodwin , Paul Geoffrey Lowney
发明人： Sharon Lea Smith , David Paul Hunter , Robert Cohn , David W. Goodwin , Paul Geoffrey Lowney
IPC分类号： G06F945
CPC分类号： G06F8/70
摘要： Computer method and apparatus allows instrumentation of program modules while maintaining exception-handling unwinding context. In the case of instrumenting procedure prologues, the invention preserves the calling context. A sanitized copy of the prologue and rewind instructions to reverse the effects of duplicate prologue instructions are employed.
摘要翻译：计算机方法和装置允许对程序模块进行检测，同时保持异常处理解卷的上下文。在调试程序序言的情况下，本发明保留了呼叫上下文。采用了序列化和反绕指令来消除重复序言指令的影响的消毒副本。

2. 发明授权

US06324689B1 Mechanism for re-writing an executable having mixed code and data 有权
标题翻译：重写具有混合代码和数据的可执行文件的机制
公开(公告)号：US06324689B1
公开(公告)日：2001-11-27
申请号：US09164255
申请日：1998-09-30
申请人： Paul Geoffrey Lowney , David William Goodwin , Robert Cohn
发明人： Paul Geoffrey Lowney , David William Goodwin , Robert Cohn
IPC分类号： G06F945
CPC分类号： G06F8/4442
摘要： A method for permitting software optimization tools, software instrumenting tools and other analysis tools to re-write executables having mixed instructions and data uses a data structure having an entry for each multi-bit word in an executable file. Each entry of the data structure includes a number of flags that are set to identify the type of the multi-bit word in the associated line of the executable file. The types include instruction, data and unclassified. Each entry also includes a flag that indicates that the multi-bit word should not be optimized and a flag indicating that the multi-bit word is a problem branch. The no-optimize and problem branch flags may be used to identify multi-bit words that may be either branch instructions or data, and to ensure that such multi-bit words are not affected by optimization or other rewriting of the executable. In addition, a problem fall through flag is provided to maintain program flow for possible fall through code segments.
摘要翻译：允许软件优化工具，软件测试工具和其他分析工具来重写具有混合指令和数据的可执行程序的方法使用具有可执行文件中的每个多位字的条目的数据结构。数据结构的每个条目包括多个标志，其被设置为标识可执行文件的相关行中的多位字的类型。类型包括指令，数据和未分类。每个条目还包括一个标志，表示多位字不应该被优化，一个标志指示多位字是一个问题分支。不优化和问题分支标志可以用于识别可以是分支指令或数据的多位字，并且确保这样的多位字不受可执行文件的优化或其他重写的影响。此外，提供了一个问题跌倒标志，以保持程序流程，以便可能落后于代码段。

3. 发明授权

US5901308A Software mechanism for reducing exceptions generated by speculatively scheduled instructions 失效
标题翻译：用于减少由推测性安排的指令产生的异常的软件机制
公开(公告)号：US5901308A
公开(公告)日：1999-05-04
申请号：US617014
申请日：1996-03-18
申请人： Robert Cohn , Michael C. Adler , Paul Geoffrey Lowney
发明人： Robert Cohn , Michael C. Adler , Paul Geoffrey Lowney
IPC分类号： G06F9/38 , G06F9/45 , G06F11/34 , G06F9/00
CPC分类号： G06F8/445 , G06F11/3466 , G06F9/3842 , G06F9/3861
摘要： A method of compiling an application to reduce the occurrence of speculative exceptions is described. The method includes the steps of compiling the application to provide a speculation table and an executable file, and obtaining profile information about said compiled application using representative data sets. The compiler includes a scheduler unit for rearranging the order of the instructions in the application to provide optimal performance. The speculation table comprises a number of entries corresponding to the instructions of the application, each entry including a tag identifying the instruction and a semaphore indicating whether or not the instruction is likely to cause an exception. The executable file is run using a number of representative data sets to profile information identifying those instructions that result in exceptions, and the tag of the instruction is stored in a log file. After the profiling has completed, the tags of the instructions causing exceptions are used to set the semaphores in the speculation table corresponding to the tag. The application is then re-compiled. During the recompilation, those instructions with their semaphores set; i.e. those instructions causing exceptions, will not be speculatively scheduled by the compiler.
摘要翻译：描述了一种编译应用程序以减少投机异常发生的方法。该方法包括编译应用程序以提供猜测表和可执行文件的步骤，以及使用代表性数据集获取关于所述编译应用的简档信息。编译器包括用于重新排列应用程序中的指令的顺序以提供最佳性能的调度器单元。推测表包括与应用程序的指令对应的多个条目，每个条目包括标识指令的标签和指示该指令是否可能引起异常的信号量。可执行文件使用许多代表性数据集进行运行，以便对识别导致异常的那些指令进行简档信息，并将指令的标签存储在日志文件中。分析完成后，导致异常的指令的标签用于设置与标签对应的推测表中的信号量。然后应用程序被重新编译。在重新编译期间，设置了它们的信号量的指令; 即导致异常的那些指令不会被编译器推测地调度。

4. 发明授权

US6163821A Method and apparatus for balancing load vs. store access to a primary data cache 有权
标题翻译：用于平衡负载与对主数据高速缓存的存储访问的方法和装置
公开(公告)号：US6163821A
公开(公告)日：2000-12-19
申请号：US215354
申请日：1998-12-18
申请人： James B. Keller , Richard E. Kessler , Stephen C. Root , Paul Geoffrey Lowney
发明人： James B. Keller , Richard E. Kessler , Stephen C. Root , Paul Geoffrey Lowney
IPC分类号： G06F9/312 , G06F9/38 , G06F13/20 , G06F13/16 , G06F13/362
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： A computer method and apparatus causes the load-store instruction grouping in a microprocessor instruction pipeline to be disrupted at appropriate times. The computer method and apparatus employs a memory access member which periodically stalls the issuance of store instructions when there are prior store instructions pending in the store queue. The periodic stalls bias the issue stage to issue load groups and store instruction groups. In the latter case, the store queue is free to update the data cache with the data from previous store instructions. Thus, the invention memory access member biases issuance of store instructions in a manner that prevents the store queue from becoming full, and as such enables the store queue to write to the data cache before the store queue becomes full.
摘要翻译：计算机方法和装置使得微处理器指令流水线中的加载存储指令分组在适当的时间被中断。计算机方法和装置采用存储器访问部件，当在存储队列中存在先前的存储指令时，周期性地停止发布存储指令。周期性档位偏离问题阶段以发布加载组并存储指令组。在后一种情况下，存储队列可以使用来自先前存储指令的数据来自由地更新数据高速缓存。因此，本发明的存储器访问部件以防止存储队列变满的方式偏移存储指令的发布，并且因此使存储队列在存储队列变满之前写入数据高速缓存。

5. 发明授权

US5923863A Software mechanism for accurately handling exceptions generated by instructions scheduled speculatively due to branch elimination 失效
标题翻译：用于精确处理由于分支消除而推测的指令生成的异常的软件机制
公开(公告)号：US5923863A
公开(公告)日：1999-07-13
申请号：US548114
申请日：1995-10-25
申请人： Michael C. Adler , Steven O. Hobbs , Paul Geoffrey Lowney
发明人： Michael C. Adler , Steven O. Hobbs , Paul Geoffrey Lowney
IPC分类号： G06F9/38 , G06F9/45
CPC分类号： G06F9/3865 , G06F8/443 , G06F8/445 , G06F9/30072 , G06F9/3842
摘要： Methods for handling exceptions caused by speculatively scheduled instructions or predicated instructions executed within a computer program are described. The method for speculatively scheduled instructions includes checking at a commit point of a speculatively scheduled instruction, a semaphore associated with the speculatively scheduled instruction and branching to an error handling routine if the semaphore is set. A set semaphore indicates that an exception occurred when the speculatively scheduled instruction was executed. For a predicated instruction the method includes checking a predicate of an eliminated branch and a semaphore associated with the speculative instruction at a commit point of the speculative instruction and branching to an error handling routine if the semaphore indicates that an exception occurred when said speculative instruction was executed, and the predicate is true, which indicates that said speculative instruction was properly executed.
摘要翻译：描述用于处理在计算机程序中执行的由推测性调度的指令或预测指令引起的异常的方法。用于推测性调度指令的方法包括在推测性调度指令的提交点处检查与所述推测性调度指令相关联的信号量，并且如果设置了所述信号量则将其分支到错误处理例程。设置的信号量指示执行推测性调度指令时发生异常。对于预测指令，该方法包括在推测性指令的提交点处检查被排除的分支和与推测指令相关联的信号量的谓词，并分支到错误处理例程，如果信号量指示当所述推测指令为执行，谓词为true，表示所述推测指令已正确执行。

6. 发明申请

US20100156888A1 Adaptive mapping for heterogeneous processing systems 审中-公开
标题翻译：异构处理系统的自适应映射
公开(公告)号：US20100156888A1
公开(公告)日：2010-06-24
申请号：US12317450
申请日：2008-12-23
申请人： Chi-Keung Luk , Paul Geoffrey Lowney
发明人： Chi-Keung Luk , Paul Geoffrey Lowney
IPC分类号： G06T1/00
CPC分类号： G06T1/20
摘要： Embodiments of a system, program product and method are presented to perform automatic partitioning of work between host processor (such as, e.g., a CPU) and at least one additional heterogeneous processing element (such as, e.g., a GPU) through run-time adaptive mapping. The adaptive mapping may be performed by a dynamic compiler, based on projected execution times predicted by curve fitting based on actual execution times generated during a profile run of the program. Other embodiments are described and claimed.
摘要翻译：呈现系统，程序产品和方法的实施例，以通过运行时间来执行主处理器（例如，CPU）和至少一个附加异构处理元件（例如，GPU）之间的工作的自动分区自适应映射。基于基于在程序的轮廓运行期间产生的实际执行时间的曲线拟合所预测的执行时间，动态编译器可以执行自适应映射。描述和要求保护其他实施例。

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