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1. 发明申请

US20050064670A1 Depletion drain-extended MOS transistors and methods for making the same 有权
标题翻译：消耗漏极扩展MOS晶体管及其制造方法
公开(公告)号：US20050064670A1
公开(公告)日：2005-03-24
申请号：US10669111
申请日：2003-09-23
申请人： Shanjen Pan , James Todd , Sameer Pendharkar , Tsutomu Kubota , Pinghai Hao
发明人： Shanjen Pan , James Todd , Sameer Pendharkar , Tsutomu Kubota , Pinghai Hao
IPC分类号： H01L21/336 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/45 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66659 , H01L29/0653 , H01L29/0847 , H01L29/0852 , H01L29/1033 , H01L29/1083 , H01L29/1087 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/7835
摘要： Depletion drain-extended MOS transistor devices and fabrication methods for making the same are provided, in which a compensated channel region is provided with p and n type dopants to facilitate depletion operation at Vgs=0, and an adjust region is implanted in the substrate proximate the channel side end of the thick gate dielectric structure for improved breakdown voltage rating. The compensated channel region is formed by overlapping implants for an n-well and a p-well, and the adjust region is formed using a Vt adjust implant with a mask exposing the adjust region.
摘要翻译：提供消耗漏极扩展MOS晶体管器件及其制造方法，其中补偿沟道区域设置有p型和n型掺杂剂以便于在Vgs = 0时耗尽操作，并且将调整区域注入到衬底中厚栅电介质结构的通道侧端用于提高击穿电压额定值。补偿通道区域由n阱和p阱的重叠植入物形成，并且使用具有暴露调整区域的掩模的Vt调整植入物形成调整区域。

2. 发明授权

US07005354B2 Depletion drain-extended MOS transistors and methods for making the same 有权
标题翻译：消耗漏极扩展MOS晶体管及其制造方法
公开(公告)号：US07005354B2
公开(公告)日：2006-02-28
申请号：US10669111
申请日：2003-09-23
申请人： Shanjen Pan , James R. Todd , Sameer Pendharkar , Tsutomu Kubota , Pinghai Hao
发明人： Shanjen Pan , James R. Todd , Sameer Pendharkar , Tsutomu Kubota , Pinghai Hao
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L29/66659 , H01L29/0653 , H01L29/0847 , H01L29/0852 , H01L29/1033 , H01L29/1083 , H01L29/1087 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/7835
摘要： Depletion drain-extended MOS transistor devices and fabrication methods for making the same are provided, in which a compensated channel region is provided with p and n type dopants to facilitate depletion operation at Vgs=0, and an adjust region is implanted in the substrate proximate the channel side end of the thick gate dielectric structure for improved breakdown voltage rating. The compensated channel region is formed by overlapping implants for an n-well and a p-well, and the adjust region is formed using a Vt adjust implant with a mask exposing the adjust region.
摘要翻译：提供消耗漏极扩展MOS晶体管器件及其制造方法，其中补偿沟道区域设置有p型和n型掺杂剂以便于在Vgs = 0时耗尽操作，并且将调整区域注入到衬底中厚栅电介质结构的通道侧端用于提高击穿电压额定值。补偿通道区域由n阱和p阱的重叠植入物形成，并且使用具有暴露调整区域的掩模的Vt调整植入物形成调整区域。

3. 发明申请

US20060286741A1 Methods of fabricating high voltage devices 有权
标题翻译：制造高压器件的方法
公开(公告)号：US20060286741A1
公开(公告)日：2006-12-21
申请号：US11154431
申请日：2005-06-16
申请人： Shanjen Pan , Sameer Pendharkar , Pinghai Hao , James Todd
发明人： Shanjen Pan , Sameer Pendharkar , Pinghai Hao , James Todd
IPC分类号： H01L21/8244
CPC分类号： H01L27/0629 , H01L29/1083 , H01L29/402 , H01L29/66659 , H01L29/7835
摘要： Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well regions are formed in the semiconductor substrate. Drain extension regions are formed in the well regions. A gate dielectric layer is formed over the device. A gate electrode layer is formed that serves as the gate electrode and a bottom capacitor plate. The gate electrode and the gate dielectric layer are patterned to form gate structures. Source and drain regions are formed within the well regions and the drain extension regions. A silicide blocking layer is formed that also serves as a capacitor dielectric. Field plates and a top capacitor plate are formed on the blocking layer.
摘要翻译：制造方法和器件包括在电容器形成期间形成的场板。在半导体衬底中形成隔离结构。在半导体衬底中形成阱区。在阱区域中形成漏极延伸区域。在器件上形成栅极电介质层。形成用作栅电极和底电容器板的栅极电极层。对栅极电极和栅极介电层进行图案化以形成栅极结构。源区和漏区形成在阱区和漏极延伸区内。形成也用作电容器电介质的硅化物阻挡层。在阻挡层上形成场板和顶部电容器板。

4. 发明授权

US07235451B2 Drain extended MOS devices with self-aligned floating region and fabrication methods therefor 有权
标题翻译：排水扩展MOS器件具有自对准浮动区域及其制造方法
公开(公告)号：US07235451B2
公开(公告)日：2007-06-26
申请号：US10378402
申请日：2003-03-03
申请人： Pinghai Hao , Shanjen Pan , Sameer Pendharkar
发明人： Pinghai Hao , Shanjen Pan , Sameer Pendharkar
IPC分类号： H01L21/336
CPC分类号： H01L29/66659 , H01L29/0615 , H01L29/0619 , H01L29/0847 , H01L29/7835
摘要： Semiconductor devices and manufacturing methods therefor are disclosed, in which a drain-extended MOS transistor comprises a self-aligned floating region proximate one end of the transistor gate and doped with a first type dopant to reduce channel hot carrier degradation, as well as an oppositely doped first source/drain laterally spaced from the first end of the gate structure in a semiconductor body. The device may further comprise a resurf region doped to a lower concentration than the floating region to facilitate improved breakdown voltage performance. A method of fabricating a drain-extended MOS transistor in a semiconductor device is disclosed, comprising providing first dopants to a floating region in a semiconductor body, which is self-aligned with the first end of a gate structure, and providing second dopants to source/drains of the semiconductor body, wherein the first and second dopants are different.
摘要翻译：公开了半导体器件及其制造方法，其中漏极扩展MOS晶体管包括靠近晶体管栅极的一端的自对准浮置区，并掺杂有第一类型掺杂剂以减少通道热载流子劣化，以及相反地掺杂的第一源极/漏极在半导体本体中与栅极结构的第一端横向间隔开。该器件还可以包括掺杂到比浮置区域更低的浓度的复现区域，以便于改进的击穿电压性能。公开了一种在半导体器件中制造漏极扩展MOS晶体管的方法，包括：向半导体本体中的浮置区域提供第一掺杂物，所述浮置区域与栅极结构的第一端自对准，并提供第二掺杂剂到源极 /半导体主体的漏极，其中第一和第二掺杂剂是不同的。

5. 发明授权

US07135373B2 Reduction of channel hot carrier effects in transistor devices 有权
公开(公告)号：US07135373B2
公开(公告)日：2006-11-14
申请号：US10670434
申请日：2003-09-23
申请人： Pinghai Hao , Shanjen Pan , Sameer Pendharkar
发明人： Pinghai Hao , Shanjen Pan , Sameer Pendharkar
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L21/26586 , H01L29/6659 , H01L29/7833
摘要： A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a transistor structure includes implanting a first dopant into a lightly doped drain (LDD) region to form a shallow region therein. The first dopant penetrates the substrate to a depth that is less than the LDD junction depth. A second dopant is implanted into the substrate beyond the LDD junction depth to form a source/drain region. The implantation of the second dopant overpowers a substantial portion of the first dopant to define a floating ring in the LDD region that mitigates channel hot carrier effects.

6. 发明授权

US07208364B2 Methods of fabricating high voltage devices 有权
标题翻译：制造高压器件的方法
公开(公告)号：US07208364B2
公开(公告)日：2007-04-24
申请号：US11154431
申请日：2005-06-16
申请人： Shanjen Pan , Sameer Pendharkar , Pinghai Hao , James R. Todd
发明人： Shanjen Pan , Sameer Pendharkar , Pinghai Hao , James R. Todd
IPC分类号： H01L21/8238
CPC分类号： H01L27/0629 , H01L29/1083 , H01L29/402 , H01L29/66659 , H01L29/7835
摘要： Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well regions are formed in the semiconductor substrate. Drain extension regions are formed in the well regions. A gate dielectric layer is formed over the device. A gate electrode layer is formed that serves as the gate electrode and a bottom capacitor plate. The gate electrode and the gate dielectric layer are patterned to form gate structures. Source and drain regions are formed within the well regions and the drain extension regions. A silicide blocking layer is formed that also serves as a capacitor dielectric. Field plates and a top capacitor plate are formed on the blocking layer.
摘要翻译：制造方法和器件包括在电容器形成期间形成的场板。在半导体衬底中形成隔离结构。在半导体衬底中形成阱区。在阱区域中形成漏极延伸区域。在器件上形成栅极电介质层。形成用作栅电极和底电容器板的栅极电极层。对栅极电极和栅极介电层进行图案化以形成栅极结构。源区和漏区形成在阱区和漏极延伸区内。形成也用作电容器电介质的硅化物阻挡层。在阻挡层上形成场板和顶部电容器板。

7. 发明申请

US20050215018A1 Reduction of channel hot carrier effects in transistor devices 有权
标题翻译：降低晶体管器件中的通道热载流子效应
公开(公告)号：US20050215018A1
公开(公告)日：2005-09-29
申请号：US11135544
申请日：2005-05-24
申请人： Pinghai Hao , Shanjen Pan , Sameer Pendharkar
发明人： Pinghai Hao , Shanjen Pan , Sameer Pendharkar
IPC分类号： H01L21/265 , H01L21/336 , H01L21/338 , H01L29/02 , H01L29/08 , H01L29/78 , H01L47/00
CPC分类号： H01L29/0847 , H01L21/26586 , H01L29/6659 , H01L29/7833
摘要： A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a transistor structure includes implanting a first dopant into a lightly doped drain (LDD) region to form a shallow region therein. The first dopant penetrates the substrate to a depth that is less than the LDD junction depth. A second dopant is implanted into the substrate beyond the LDD junction depth to form a source/drain region. The implantation of the second dopant overpowers a substantial portion of the first dopant to define a floating ring in the LDD region that mitigates channel hot carrier effects.
摘要翻译：可以制造晶体管以显示减少的通道热载体效应。根据本发明的一个方面，制造晶体管结构的方法包括将第一掺杂剂注入到轻掺杂漏极（LDD）区域中以在其中形成浅区域。第一掺杂剂将衬底渗透至小于LDD结深度的深度。将第二掺杂剂注入超过LDD结深度的衬底中以形成源/漏区。第二掺杂剂的注入超过第一掺杂剂的大部分，以限定LDD区域中的浮动环，其缓和了通道热载流子效应。

8. 发明授权

US07122862B2 Reduction of channel hot carrier effects in transistor devices 有权
标题翻译：降低晶体管器件中的通道热载流子效应
公开(公告)号：US07122862B2
公开(公告)日：2006-10-17
申请号：US11135544
申请日：2005-05-24
申请人： Pinghai Hao , Shanjen Pan , Sameer Pendharkar
发明人： Pinghai Hao , Shanjen Pan , Sameer Pendharkar
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L21/26586 , H01L29/6659 , H01L29/7833
摘要： A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a transistor structure includes implanting a first dopant into a lightly doped drain (LDD) region to form a shallow region therein. The first dopant penetrates the substrate to a depth that is less than the LDD junction depth. A second dopant is implanted into the substrate beyond the LDD junction depth to form a source/drain region. The implantation of the second dopant overpowers a substantial portion of the first dopant to define a floating ring in the LDD region that mitigates channel hot carrier effects.
摘要翻译：可以制造晶体管以显示减少的通道热载体效应。根据本发明的一个方面，制造晶体管结构的方法包括将第一掺杂剂注入到轻掺杂漏极（LDD）区域中以在其中形成浅区域。第一掺杂剂将衬底渗透至小于LDD结深度的深度。将第二掺杂剂注入超过LDD结深度的衬底中以形成源/漏区。第二掺杂剂的注入超过第一掺杂剂的大部分，以限定LDD区域中的浮动环，其缓和了通道热载流子效应。

9. 发明申请

US20050064671A1 Reduction of channel hot carrier effects in transistor devices 有权
公开(公告)号：US20050064671A1
公开(公告)日：2005-03-24
申请号：US10670434
申请日：2003-09-23
申请人： Pinghai Hao , Shanjen Pan , Sameer Pendharkar
发明人： Pinghai Hao , Shanjen Pan , Sameer Pendharkar
IPC分类号： H01L21/265 , H01L21/336 , H01L21/338 , H01L29/02 , H01L29/08 , H01L29/78 , H01L47/00
CPC分类号： H01L29/0847 , H01L21/26586 , H01L29/6659 , H01L29/7833
摘要： A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a transistor structure includes implanting a first dopant into a lightly doped drain (LDD) region to form a shallow region therein. The first dopant penetrates the substrate to a depth that is less than the LDD junction depth. A second dopant is implanted into the substrate beyond the LDD junction depth to form a source/drain region. The implantation of the second dopant overpowers a substantial portion of the first dopant to define a floating ring in the LDD region that mitigates channel hot carrier effects.

10. 发明申请

US20060170056A1 Drain extended PMOS transistor with increased breakdown voltage 有权
标题翻译：以增加的击穿电压漏极扩展PMOS晶体管
公开(公告)号：US20060170056A1
公开(公告)日：2006-08-03
申请号：US11047418
申请日：2005-01-31
申请人： Shanjen Pan , Sameer Pendharkar , James Todd
发明人： Shanjen Pan , Sameer Pendharkar , James Todd
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L29/0878 , H01L29/1083 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device (102) that includes a drain extended PMOS transistor (CT1a) is provided, as well as fabrication methods (202) therefore. In forming the PMOS transistor, a drain (124) of the transistor is formed over a region (125) of a p-type upper epitaxial layer (106), where the region (125) of the p-type upper epitaxial layer (106) is sandwiched between a left P-WELL region (130a) and a right P-WELL region (130b) formed within the p-type upper epitaxial layer (106). The p-type upper epitaxial layer (106) is formed over a semiconductor body (104) that has an n-buried layer (108) formed therein. This arrangement serves to increase the breakdown voltage (BVdss) of the drain extended PMOS transistor.
摘要翻译：提供了包括漏极延伸PMOS晶体管（CT1a）的半导体器件（102），以及制造方法（202）。在形成PMOS晶体管时，晶体管的漏极（124）形成在p型上部外延层（106）的区域（125）上，其中p型上部外延层（106）的区域（125））夹在形成在p型上部外延层（106）内的左P-WELL区域（130a）和右P-WELL区域（130b）之间。 p型上部外延层（106）形成在其上形成有n埋层（108）的半导体本体（104）上。这种布置用于增加漏极延伸PMOS晶体管的击穿电压（BVdss）。

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