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1. 发明授权

US06525966B1 Method and apparatus for adjusting on-chip current reference for EEPROM sensing 有权
标题翻译：用于调整EEPROM感应的片内电流参考的方法和装置
公开(公告)号：US06525966B1
公开(公告)日：2003-02-25
申请号：US10010985
申请日：2001-12-05
申请人： Shane C. Hollmer , Joseph G. Pawletko , Binh Quang Le
发明人： Shane C. Hollmer , Joseph G. Pawletko , Binh Quang Le
IPC分类号： G11C1606
CPC分类号： G11C16/26 , G11C16/06
摘要： Method and apparatus for a memory circuit having a sense amplifier circuit having a sensing amplifier connected to read the data content output of a memory cell where the sense amplifier circuit includes a current source transistor having a gate terminal and having a drain terminal connected to a voltage supply and having a source terminal connected to the sensing amplifier, with a selectable source current in order to account for variation from a desired source current due to variations in the designed source current transistor performance parameters.
摘要翻译：一种具有读出放大器电路的存储电路的方法和装置，该读出放大器电路具有连接到读出存储单元的数据内容输出的感测放大器，其中读出放大器电路包括具有栅极端子并具有连接到电压的漏极端子的电流源晶体管提供并具有连接到感测放大器的源极端子，具有可选择的源极电流，以便考虑到由于设计的源极电流晶体管性能参数的变化而导致的期望源极电流的变化。

2. 发明授权

US06295228B1 System for programming memory cells 有权
标题翻译：用于编程存储单元的系统
公开(公告)号：US06295228B1
公开(公告)日：2001-09-25
申请号：US09514933
申请日：2000-02-28
申请人： Joseph G. Pawletko , Binh Quang Le , Pau-Ling Chen , James M. Hong
发明人： Joseph G. Pawletko , Binh Quang Le , Pau-Ling Chen , James M. Hong
IPC分类号： G11C1606
CPC分类号： G11C29/028 , G11C16/04 , G11C16/10 , G11C16/30 , G11C29/50 , G11C2029/5004
摘要： A programming control circuit programs a memory cell in accordance to a programming signal value that can be varied by a test equipment. The programming control circuit comprises a signal storage device, a signal output circuit, and a verification circuit. The signal storage device stores the programming signal value. The test equipment can be coupled to the signal storage device to write the programming signal value into the signal storage device. The signal output circuit is coupled to the signal storage device to receive the programming signal value. The signal output circuit converts the programming signal value into a programming signal and outputs the programming signal to the memory cell. The verification circuit determines whether the memory cell is successfully programmed. If the memory cell is not successfully programmed, the programming control circuit increases the programming signal value.
摘要翻译：编程控制电路根据可由测试设备改变的编程信号值对存储器单元进行编程。编程控制电路包括信号存储装置，信号输出电路和验证电路。信号存储装置存储编程信号值。测试设备可以耦合到信号存储设备，以将编程信号值写入信号存储设备。信号输出电路耦合到信号存储装置以接收编程信号值。信号输出电路将编程信号值转换为编程信号，并将编程信号输出到存储单元。验证电路确定存储器单元是否被成功编程。如果存储单元未成功编程，编程控制电路会增加编程信号值。

3. 发明授权

US06304487B1 Register driven means to control programming voltages 有权
标题翻译：寄存器驱动方式来控制编程电压
公开(公告)号：US06304487B1
公开(公告)日：2001-10-16
申请号：US09514404
申请日：2000-02-28
申请人： Joseph G. Pawletko , Binh Quang Le , Pau-Ling Chen , James M. Hong
发明人： Joseph G. Pawletko , Binh Quang Le , Pau-Ling Chen , James M. Hong
IPC分类号： G11C1606
CPC分类号： G11C16/12 , G11C16/10 , G11C16/3436
摘要： A voltage control circuit that programs or erases memory cells comprises an internal voltage value store, a register device selectively coupled to an external voltage value source or the internal voltage value store to receive a voltage value, a voltage output circuit coupled to the register device to receive the voltage value and to output a corresponding voltage to the memory cells, and a verify circuit determining the time to successfully program or erase the memory cells. The register device allows the memory cells to be programmed or erased with voltage values designated by the external voltage value source to determine programming and erasing characteristics of the memory cells. Voltage values producing acceptable programming and erasing characteristics are saved in the internal voltage value store.
摘要翻译：编程或擦除存储器单元的电压控制电路包括内部电压值存储器，选择性地耦合到外部电压值源的寄存器器件或用于接收电压值的内部电压值存储器，耦合到寄存器器件的电压输出电路，接收电压值并将相应的电压输出到存储器单元，以及确认电路确定成功编程或擦除存储单元的时间。寄存器件允许用由外部电压值源指定的电压值对存储器单元进行编程或擦除，以确定存储器单元的编程和擦除特性。产生可接受的编程和擦除特性的电压值被保存在内部电压值存储器中。

4. 发明授权

US06246611B1 System for erasing a memory cell 有权
标题翻译：擦除存储单元的系统
公开(公告)号：US06246611B1
公开(公告)日：2001-06-12
申请号：US09514560
申请日：2000-02-28
申请人： Joseph G. Pawletko , Binh Quang Le , James M. Hong , Pau-Ling Chen
发明人： Joseph G. Pawletko , Binh Quang Le , James M. Hong , Pau-Ling Chen
IPC分类号： G11C1600
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/344
摘要： An erase control circuit erases a memory cell in accordance to an erase signal value that can be varied by a test equipment. The erase control circuit comprises a signal storage device, a signal output circuit, and a verification circuit. The signal storage device stores the erase signal value. A test equipment can be coupled to the signal storage device to write the programming signal value into the signal storage device. The signal output circuit is coupled to the signal storage device to receive the erase signal value. The signal output circuit converts the erase signal value into an erase signal and outputs the erase signal to the memory cell. The verification circuit determines whether the memory cell is successfully erased. If the memory cell is not successfully erased, the erase control circuit increases the erase signal value.
摘要翻译：擦除控制电路根据可由测试设备改变的擦除信号值来擦除存储单元。擦除控制电路包括信号存储装置，信号输出电路和验证电路。信号存储装置存储擦除信号值。测试设备可以耦合到信号存储设备，以将编程信号值写入信号存储设备。信号输出电路耦合到信号存储装置以接收擦除信号值。信号输出电路将擦除信号值转换成擦除信号，并将该擦除信号输出到存储单元。验证电路确定存储器单元是否被成功擦除。如果存储单元未成功擦除，则擦除控制电路增加擦除信号值。

5. 发明授权

US06181605B2 Global erase/program verification apparatus and method 有权
标题翻译：全局擦除/程序验证装置和方法
公开(公告)号：US06181605B2
公开(公告)日：2001-01-30
申请号：US09414750
申请日：1999-10-06
申请人： Shane C. Hollmer , Joseph G. Pawletko , Michael S. C. Chung
发明人： Shane C. Hollmer , Joseph G. Pawletko , Michael S. C. Chung
IPC分类号： G11C1606
CPC分类号： G11C16/3445 , G11C16/0483 , G11C16/3436 , G11C16/3459
摘要： A technique to determine whether multiple memory cells are programmed or erased. After a program or erase operation, respective program or erase verify operations are performed. A logical gate is coupled to measure the state of each memory cell. When all memory cells selected to be programmed or erased are programmed or erased then the output of the logical gate indicates successful program or erase verify. Thus, by using a single logical gate coupled to measure the states of multiple memory cells, only the output of the logical gate need be measured to determine successful program or erase verification of multiple memory cells.
摘要翻译：确定多个存储器单元是否被编程或擦除的技术。在编程或擦除操作之后，执行相应的编程或擦除验证操作。耦合逻辑门来测量每个存储单元的状态。当所有被选择被编程或擦除的存储单元被编程或擦除时，逻辑门的输出指示成功的程序或擦除验证。因此，通过使用耦合以测量多个存储器单元的状态的单个逻辑门，仅需要测量逻辑门的输出以确定多个存储单元的成功编程或擦除验证。

6. 发明授权

US06545912B1 Erase verify mode to evaluate negative Vt's 有权
标题翻译：擦除验证模式来评估负Vt
公开(公告)号：US06545912B1
公开(公告)日：2003-04-08
申请号：US09727656
申请日：2000-11-30
申请人： Joseph G. Pawletko , Shane C. Hollmer , Pau-Ling Chen
发明人： Joseph G. Pawletko , Shane C. Hollmer , Pau-Ling Chen
IPC分类号： G11C1606
CPC分类号： G11C29/50004 , G11C16/04 , G11C16/344 , G11C29/50
摘要： A method is provided to determine erase threshold voltages of memory transistors and thereby identify unusable memory transistors. A voltage is applied to the common source of a selected memory transistor and gradually incremented until a logical HIGH bit is read as a logical LOW bit. By iteratively incrementing Vbias, the erase threshold voltage for each memory transistor can be determined. In one process, the erase threshold voltage for each memory transistor in a memory device is determined and then the memory device is put under stress tests to simulate normal operative conditions. After the stress tests, the erase threshold voltage of each memory transistor can be once again determined to ascertain the change in the erase threshold voltage, i.e., the data retention characteristic, of each memory transistor.
摘要翻译：提供了一种方法来确定存储晶体管的擦除阈值电压，从而识别不可用的存储晶体管。电压被施加到所选择的存储晶体管的公共源，并逐渐增加，直到逻辑高位被读为逻辑低位。通过迭代地增加Vbias，可以确定每个存储晶体管的擦除阈值电压。在一个过程中，确定存储器件中每个存储晶体管的擦除阈值电压，然后将存储器件置于压力测试中以模拟正常工作状态。在应力测试之后，可以再次确定每个存储晶体管的擦除阈值电压，以确定每个存储晶体管的擦除阈值电压（即数据保持特性）的变化。

7. 发明授权

US06185130B2 Programmable current source 有权
标题翻译：可编程电流源
公开(公告)号：US06185130B2
公开(公告)日：2001-02-06
申请号：US09420209
申请日：1999-10-18
申请人： Shane C. Hollmer , Joseph G. Pawletko
发明人： Shane C. Hollmer , Joseph G. Pawletko
IPC分类号： G11C1606
CPC分类号： G11C16/24 , G11C5/147 , G11C16/3436 , G11C29/12
摘要： A programmable reference current source used with a memory array during test and user modes to program or erase verify. The reference current source is programmable so that optimal reference currents can be determined during test mode. A value representing the optimal reference current is stored so that the reference current source provides the determined reference current during user mode.
摘要翻译：在测试期间与存储器阵列一起使用的可编程参考电流源，并且用户模式编程或擦除验证。参考电流源可编程，以便在测试模式下可以确定最佳的参考电流。存储表示最佳参考电流的值，使得参考电流源在用户模式期间提供确定的参考电流。

8. 发明授权

US06246610B1 Symmetrical program and erase scheme to improve erase time degradation in NAND devices 有权
标题翻译：对称编程和擦除方案，以改善NAND器件中的擦除时间退化
公开(公告)号：US06246610B1
公开(公告)日：2001-06-12
申请号：US09511652
申请日：2000-02-22
申请人： K. Michael Han , Joseph G. Pawletko , Narbeh Derhacobian , Chi Chang
发明人： K. Michael Han , Joseph G. Pawletko , Narbeh Derhacobian , Chi Chang
IPC分类号： G11C1604
CPC分类号： G11C16/14 , G11C16/10 , G11C16/30
摘要： A programming and erase method that extends erase time degradation of nonvolatile memory devices by using a constant erase voltage and a set of program voltages, where the average program voltage of the set of the program voltages is approximately equal to the constant erase voltage.
摘要翻译：一种编程和擦除方法，其通过使用恒定擦除电压和一组编程电压来延长非易失性存储器件的擦除时间劣化，其中编程电压组的平均编程电压近似等于恒定擦除电压。

9. 发明授权

US5335198A Flash EEPROM array with high endurance 失效
标题翻译：闪存EEPROM阵列具有高耐久性
公开(公告)号：US5335198A
公开(公告)日：1994-08-02
申请号：US57583
申请日：1993-05-06
申请人： Michael A. Van Buskirk , Kevin W. Plouse , Joseph G. Pawletko , Chi Chang , Sameer S. Haddad , Ravi P. Gutala
发明人： Michael A. Van Buskirk , Kevin W. Plouse , Joseph G. Pawletko , Chi Chang , Sameer S. Haddad , Ravi P. Gutala
IPC分类号： G11C16/28 , G11C16/34 , G11C29/00 , G11C29/02 , G11C29/50
CPC分类号： G11C29/82 , G11C16/28 , G11C16/3404 , G11C16/3409 , G11C29/02 , G11C29/025 , G11C29/50 , G11C29/88 , G11C16/04 , G11C2029/5006
摘要： An over-erased bit correction structure is provided for performing a correction operation on over-erased memory cells in an array of flash EEPROM memory cells during programming operations so as to render high endurance. Sensing circuitry (23) is used to detect column leakage current indicative of an over-erased bit. If an over-erased bit is determined, a pulse counter (25) is activated so as to apply programming pulses to the control gate of the selected memory cell so as to program back the negative threshold voltage of the over-erased bit to a positive voltage.
摘要翻译：提供了一种过擦除位校正结构，用于在编程操作期间对闪存EEPROM存储器单元阵列中的擦除过的存储器单元进行校正操作，以使其具有高耐久性。感测电路（23）用于检测指示过擦除位的列泄漏电流。如果确定了过擦除位，则激活脉冲计数器（25），以便将编程脉冲施加到所选存储单元的控制栅极，以便将过擦除位的负阈值电压反馈到正电压。

10. 发明授权

US6141244A Multi level sensing of NAND memory cells by external bias current 有权
标题翻译：通过外部偏置电流对NAND存储单元的多电平感测
公开(公告)号：US6141244A
公开(公告)日：2000-10-31
申请号：US388696
申请日：1999-09-02
申请人： Joseph G. Pawletko , Pau-Ling Chen , Shane Charles Hollmer
发明人： Joseph G. Pawletko , Pau-Ling Chen , Shane Charles Hollmer
IPC分类号： G11C11/56 , G11C16/04
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5642 , G11C2211/5642
摘要： A method and circuit for sensing multi states of a NAND memory cell by applying plurality of external sensing bias current at a constant positive gate and bias voltage and detecting a cell current wherein the cell current depends upon the state of the memory cell.
摘要翻译：一种用于通过以恒定正栅极和偏置电压施加多个外部感测偏置电流来感测NAND存储器单元的多状态并检测单元电流的方法和电路，其中单元电流取决于存储单元的状态。

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