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1. 发明授权

US5650659A Semiconductor component package assembly including an integral RF/EMI shield 失效
标题翻译：半导体元件封装组件包括一个集成的RF / EMI屏蔽
公开(公告)号：US5650659A
公开(公告)日：1997-07-22
申请号：US511391
申请日：1995-08-04
申请人： Shahram Mostafazadeh , Satya Chillara , Jagdish Belani
发明人： Shahram Mostafazadeh , Satya Chillara , Jagdish Belani
IPC分类号： H01L23/31 , H01L23/552
CPC分类号： H01L23/552 , H01L23/315 , H01L2224/32245 , H01L2224/45099 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L24/48 , H01L24/73 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/16152 , H01L2924/181 , H01L2924/3025
摘要： A semiconductor component package assembly including an integral radio frequency and electromagnetic interference shield is disclosed herein. The assembly includes a support member which supports an IC chip and defines an array of conductive leads. An electrically conductive shield is positioned relative to the IC chip so as to form an integral RF/EMI barrier between the IC chip and the ambient surroundings of the overall assembly. In a preferred embodiment, the shield is formed from different layers of material and configured for electrical connection of at least one conductive layer to certain ones of the leads which may include one or more ground leads. In a method of the invention, a shield is provided which is thereafter fixedly attached to an intermediate assembly including an IC chip to form an integral RF/EMI shield between the chip and the the ambient environment
摘要翻译：本文公开了一种包括集成射频和电磁干扰屏蔽的半导体部件封装组件。该组件包括支撑IC芯片并且限定导电引线阵列的支撑构件。导电屏蔽相对于IC芯片定位，以便在IC芯片和整个组件的周围环境之间形成整体的RF / EMI屏障。在优选实施例中，屏蔽由不同的材料层形成并且被配置为用于将至少一个导电层电连接到可以包括一个或多个接地引线的某些引线。在本发明的方法中，提供了一种屏蔽件，其后固定地附接到包括IC芯片的中间组件，以在芯片和周围环境之间形成整体的RF / EMI屏蔽

2. 发明授权

US5498901A Lead frame having layered conductive planes 失效
标题翻译：引线框架具有分层导电平面
公开(公告)号：US5498901A
公开(公告)日：1996-03-12
申请号：US294323
申请日：1994-08-23
申请人： Satya Chillara , Shahram Mostafazadeh
发明人： Satya Chillara , Shahram Mostafazadeh
IPC分类号： H01L23/495
CPC分类号： H01L24/49 , H01L23/49531 , H01L2224/05554 , H01L2224/48247 , H01L2224/49109 , H01L2224/49171 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01078 , H01L2924/01082 , H01L2924/07802 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19107 , H01L2924/30107 , H01L2924/3011
摘要： A lead frame having layered conductive planes is disclosed for use in semiconductor devices. The lead frame includes a plurality of long leads each having a lead tip and a plurality of short leads. Electrically conductive layers are attached to the long leads around such that they don't cover the tips of the long leads and are radially inward of the short leads. The conductive layers are insulated from the long lead and each other by adhesive insulating layers. In a preferred embodiment, the top conductive layer has a smaller width than the bottom conducting layer and is positioned to expose an inner and outer ledge on the bottom conducting layer. The exposed outer ledge allows bonding to the shorter leads. The use of shorter leads decreases the amount of inductance in the leads. The conductive layers also may act as capacitors. In one embodiment of the present application the short leads may correspond to ground and/or power leads. The decreased inductance and increased capacitance decreases the impedance seen in the power and ground leads. This allows the semiconductor to operate at higher speeds and consume less power.
摘要翻译：公开了一种用于半导体器件的具有分层导电平面的引线框架。引线框架包括多个长引线，每个引线具有引线端头和多个短引线。导电层被连接到长引线周围，使得它们不覆盖长引线的尖端并且在短引线的径向内侧。导电层与长引线绝缘，并且通过粘合绝缘层彼此绝缘。在优选实施例中，顶部导电层具有比底部导电层更小的宽度，并且定位成暴露底部导电层上的内部和外部凸缘。暴露的外凸缘允许结合到较短的引线。使用较短的引线会降低引线中的电感量。导电层也可以用作电容器。在本申请的一个实施例中，短引线可对应于接地和/或电源引线。降低的电感和增加的电容降低了在电源和接地引线中看到的阻抗。这允许半导体以更高的速度运行并且消耗更少的功率。

3. 发明授权

US06184575B2 Ultra-thin composite package for integrated circuits 失效
标题翻译：用于集成电路的超薄复合封装
公开(公告)号：US06184575B2
公开(公告)日：2001-02-06
申请号：US08296671
申请日：1994-08-26
申请人： Satya Chillara , Shahram Mostafazadeh
发明人： Satya Chillara , Shahram Mostafazadeh
IPC分类号： H01L23495
CPC分类号： H01L23/3121 , H01L23/49548 , H01L24/48 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/181 , H01L2224/45099 , H01L2224/05599 , H01L2924/00 , H01L2924/00012
摘要： An ultra-thin composite package for integrated circuits including a metal base with a cavity to support a die with a molded plastic cap cooperating with the base to encapsulate the die. A lead frame having a thinned inner portion or lead tip areas may also be used to further reduce the package thickness. Package thicknesses of about 20 mils (0.5 mm) or less can be readily achieved using this structure combination.
摘要翻译：一种用于集成电路的超薄复合封装，其包括具有空腔的金属基底，以支撑具有模塑塑料帽的模具，其与基底配合以封装模具。具有变薄的内部部分或引线尖端区域的引线框架也可用于进一步减小封装厚度。使用该结构组合可容易地实现约20密耳（0.5mm）或更小的封装厚度。

4. 发明授权

US5705851A Thermal ball lead integrated package 失效
标题翻译：热球铅一体化包装
公开(公告)号：US5705851A
公开(公告)日：1998-01-06
申请号：US496043
申请日：1995-06-28
申请人： Shahram Mostafazadeh , Satya Chillara , Jagdish G. Belani
发明人： Shahram Mostafazadeh , Satya Chillara , Jagdish G. Belani
IPC分类号： H01L23/31 , H01L23/433 , H01L23/495 , H01L23/10 , H01L23/34 , H01L23/48
CPC分类号： H01L23/3128 , H01L23/4334 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/49109 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/181
摘要： A Thermal Ball Lead Integrated Package (Thermal BLIP) having improved thermal performance over prior art BLIPs is described. The BLIP combines ball and lead technologies to increase the interconnect density of the package but has relatively poor heat extraction capabilities. The Thermal BLIP is particularly well suited for high power and pin count integrated circuit devices. In an embodiment of the present invention, a heat sink is attached to the top surface of the die and extends through the package molding such that it is exposed to the ambient environment. Since the heat sink is integrated into the molding, the package size and footprint is not increased thereby limiting the cost increase of the package. This arrangement enables the use of high power devices in dense circuit board applications.
摘要翻译：描述了具有比现有技术BLIP更好的热性能的热球铅集成封装（热BLIP）。 BLIP组合了球和铅技术，以增加包装的互连密度，但具有相对较差的散热能力。热BLIP特别适用于大功率和针数集成电路器件。在本发明的一个实施例中，散热器附接到模具的顶表面并延伸穿过封装模制件，使得其暴露于周围环境。由于散热器集成到模制件中，因此封装尺寸和封装不会增加，从而限制了封装的成本增加。这种布置使得能够在密集电路板应用中使用大功率器件。

5. 发明授权

US5739581A High density integrated circuit package assembly with a heatsink between stacked dies 失效
标题翻译：高密度集成电路封装组件，在堆叠裸片之间具有散热片
公开(公告)号：US5739581A
公开(公告)日：1998-04-14
申请号：US560280
申请日：1995-11-17
申请人： Satya Chillara , Shahram Mostafazadeh
发明人： Satya Chillara , Shahram Mostafazadeh
IPC分类号： H01L25/065 , H01L23/495 , H01L23/10
CPC分类号： H01L25/0657 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/49109 , H01L2224/73265 , H01L2225/0651 , H01L2225/06575 , H01L2225/06582 , H01L2225/06586 , H01L24/73 , H01L2924/01079 , H01L2924/01322 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/1627
摘要： An integrated circuit package assembly with a first die disposed over a first substrate having traces defined therein to provide electrical access to the first die. A heatsink is disposed over the substrate and the first die. A second die and a leadframe is disposed over the heatsink. The leadframe provides electrical access to the second die.
摘要翻译：一种集成电路封装组件，其具有设置在第一衬底上的第一裸片，其具有限定在其中的迹线，以提供对第一裸片的电接触。散热器设置在衬底和第一裸片上。第二管芯和引线框架设置在散热片上。引线框架提供对第二管芯的电气接入。

6. 发明授权

US5648679A Tape ball lead integrated circuit package 失效
标题翻译：磁带球导联集成电路封装
公开(公告)号：US5648679A
公开(公告)日：1997-07-15
申请号：US511395
申请日：1995-08-04
申请人： Satya Chillara , Shahram Mostafazadeh
发明人： Satya Chillara , Shahram Mostafazadeh
IPC分类号： H01L23/31 , H01L23/498 , H05K3/34 , H01L23/02
CPC分类号： H01L23/4985 , H01L23/3121 , H01L23/49816 , H01L24/49 , H05K3/341 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/49109 , H01L2224/49175 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H05K2201/10659 , H05K2201/10689 , H05K2201/10734 , Y02P70/613
摘要： An integrated circuit assembly includes a dielectric flex tape substrate defining a predetermined array of electrically conductive traces and an array of solder balls or solder columns electrically connected to the bottom surface of the flex tape substrate and the traces. An integrated circuit die having a series of input/output pads is supported on the substrate. In one embodiment, a plurality of electrically conductive leads are supported by the flex tape substrate in electrical isolation from and over the conductive traces. A first and second series of bonding wires electrically connect certain ones of the input/output terminals on the integrated circuit die to the electrically conductive leads and conductive traces, respectively. In other embodiments, one or more electrically isolated conductive layers are supported by the dielectric flex tape substrate over the traces and electrically conductive leads. The integrated circuit package assembly, in accordance with any of these embodiments, provides a very high density electrical interconnection arrangement for the integrated circuit die while retaining a small package footprint.
摘要翻译：集成电路组件包括限定预定数量的导电迹线的电介质柔性带衬底和电连接到柔性带衬底和迹线的底表面的焊球或焊料柱的阵列。具有一系列输入/输出焊盘的集成电路管芯被支撑在衬底上。在一个实施例中，多个导电引线由导电迹线与导电迹线电绝缘支撑在柔性带基片上。第一和第二系列接合线分别将集成电路管芯上的某些输入/输出端子电连接到导电引线和导电迹线。在其他实施例中，一个或多个电绝缘导电层由电介质柔性带基板支撑在迹线和导电引线上。根据这些实施例中的任何一个的集成电路封装组件为集成电路管芯提供非常高密度的电互连布置，同时保持小的封装封装。

7. 发明授权

US5569955A High density integrated circuit assembly combining leadframe leads with conductive traces 失效
公开(公告)号：US5569955A
公开(公告)日：1996-10-29
申请号：US406726
申请日：1995-03-20
申请人： Satya Chillara , Shahram Mostafazadeh
发明人： Satya Chillara , Shahram Mostafazadeh
IPC分类号： H01L23/31 , H01L23/495 , H01L23/498 , H05K3/34
CPC分类号： H01L23/49861 , H01L23/3121 , H01L23/49517 , H01L23/4985 , H01L24/49 , H05K3/341 , H01L2224/05553 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/49109 , H01L2224/49175 , H01L2224/49433 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01033 , H01L2924/01052 , H01L2924/01057 , H01L2924/01068 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/30107 , H05K2201/10659 , H05K2201/10689 , H05K2201/10734 , Y02P70/613
摘要： An integrated circuit assembly is disclosed herein. The assembly includes a dielectric substrate defining a predetermined array of electrically conductive traces and an array of solder balls electrically connected to the traces. An integrated circuit chip having a series of input/output pads is supported on the substrate. In one embodiment, a plurality of leadframe leads are supported by the substrate in electrical isolation from and over the conductive traces. First and second series of bonding wires electrically connect certain ones of the input/output pads on the IC chip to the leadframe leads and conductive traces. In other embodiments, one or more electrically isolated conductive layers are supported by the dielectric substrate over the traces and leadframe leads. The integrated circuit assembly, in accordance with any of these embodiments, provides a very high density electrical interconnection arrangement for the IC chip while retaining a small package footprint.

8. 发明授权

US5442230A High density integrated circuit assembly combining leadframe leads with conductive traces 失效
标题翻译：将引线框引线与导电迹线相结合的高密度集成电路组件
公开(公告)号：US5442230A
公开(公告)日：1995-08-15
申请号：US307270
申请日：1994-09-16
申请人： Satya Chillara , Shahram Mostafazadeh
发明人： Satya Chillara , Shahram Mostafazadeh
IPC分类号： H01L23/31 , H01L23/495 , H01L23/498 , H05K3/34 , H01L23/02
CPC分类号： H05K3/341 , H01L23/3121 , H01L23/49517 , H01L23/4985 , H01L23/49861 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/49109 , H01L2224/49175 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/30107 , H05K2201/10659 , H05K2201/10689 , H05K2201/10734 , Y02P70/613
摘要： An integrated circuit assembly is disclosed herein. The assembly includes a dielectric substrate defining a predetermined array of electrically conductive traces and an array of solder balls electrically connected to the traces. An integrated circuit chip having a series of input/output pads is supported on the substrate. In one embodiment, a plurality of leadframe leads are supported by the substrate in electrical isolation from and over the conductive traces. First and second series of bonding wires electrically connect certain ones of the input/output pads on the IC chip to the leadframe leads and conductive traces. In other embodiments, one or more electrically isolated conductive layers are supported by the dielectric substrate over the traces and leadframe leads. The integrated circuit assembly, in accordance with any of these embodiments, provides a very high density electrical interconnection arrangement for the IC chip while retaining a small package footprint.
摘要翻译：本文公开了集成电路组件。组件包括限定预定阵列的导电迹线的电介质基片和电连接到迹线的焊球阵列。具有一系列输入/输出焊盘的集成电路芯片被支撑在基板上。在一个实施例中，多个引线框引线由导电迹线与导电迹线电隔离地由衬底支撑。第一和第二系列接合线将IC芯片上的某些输入/输出焊盘电连接到引线框引线和导电迹线。在其他实施例中，一个或多个电绝缘导电层由电介质基板支撑在迹线和引线框引线上。根据这些实施例中的任何一个的集成电路组件为IC芯片提供非常高密度的电互连布置，同时保持小的封装封装。

9. 发明授权

US5627405A Integrated circuit assembly incorporating an anisotropic elecctrically conductive layer 失效
标题翻译：结合各向异性电导率层的集成电路组件
公开(公告)号：US5627405A
公开(公告)日：1997-05-06
申请号：US503302
申请日：1995-07-17
申请人： Satya Chillara
发明人： Satya Chillara
IPC分类号： H01L21/60 , H01L23/367 , H01L23/42 , H01L23/498 , H01L23/48
CPC分类号： H01L24/81 , H01L23/3675 , H01L23/42 , H01L23/49827 , H01L23/4985 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/14 , H01L2924/15311
摘要： An integrated circuit assembly includes an integrated circuit chip having a plurality of input/output terminals arranged at a surface thereof, and an electrically conductive layer connected to such surface of the integrated circuit chip. The layer is electrically conductive in thickness and electrically insulative in width and length. The assembly may further include a dielectric substrate connected to the layer such that the layer electrically connects respective terminals of the integrated circuit chip to respective electrically conductive traces of the dielectric substrate. An array of contacts may be electrically connected to the traces of the dielectric substrate.
摘要翻译：集成电路组件包括具有布置在其表面上的多个输入/输出端子的集成电路芯片和连接到集成电路芯片的这种表面的导电层。该层的厚度是导电的，并且在宽度和长度上是电绝缘的。组件还可以包括连接到该层的电介质基板，使得该层将集成电路芯片的相应端子电连接到电介质基板的相应导电迹线。触点阵列可以电连接到电介质基片的迹线。

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