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1. 发明申请

US20100088453A1 Multi-Processor Architecture and Method 有权
标题翻译：多处理器架构和方法
公开(公告)号：US20100088453A1
公开(公告)日：2010-04-08
申请号：US12340510
申请日：2008-12-19
申请人： Shahin Solki , Stephen Morein , Mark S. Grossman
发明人： Shahin Solki , Stephen Morein , Mark S. Grossman
IPC分类号： G06F13/20
CPC分类号： G06F13/4282 , G06F3/14 , G06F2213/0026 , G06T1/20 , G06T1/60 , G09G5/006 , G09G5/363 , G09G2330/021 , G09G2360/06
摘要： Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.
摘要翻译：本文描述了多处理器架构和方法的实施例。实施例提供了使用外部桥式集成电路（IC）架构的替代方案。例如，实施例复用外围总线，使得多个处理器可以使用一个外围接口插槽而不需要外部桥接IC。实施例可用于已知的总线协议。

2. 发明授权

US08373709B2 Multi-processor architecture and method 有权
标题翻译：多处理器架构和方法
公开(公告)号：US08373709B2
公开(公告)日：2013-02-12
申请号：US12340510
申请日：2008-12-19
申请人： Shahin Solki , Stephen Morein , Mark S. Grossman
发明人： Shahin Solki , Stephen Morein , Mark S. Grossman
IPC分类号： G06F15/16
CPC分类号： G06F13/4282 , G06F3/14 , G06F2213/0026 , G06T1/20 , G06T1/60 , G09G5/006 , G09G5/363 , G09G2330/021 , G09G2360/06
摘要： Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.
摘要翻译：本文描述了多处理器架构和方法的实施例。实施例提供了使用外部桥式集成电路（IC）架构的替代方案。例如，实施例复用外围总线，使得多个处理器可以使用一个外围接口插槽而不需要外部桥接IC。实施例可用于已知的总线协议。

3. 发明申请

US20100088452A1 Internal BUS Bridge Architecture and Method in Multi-Processor Systems 有权
标题翻译：多处理器系统中的内部总线桥结构和方法
公开(公告)号：US20100088452A1
公开(公告)日：2010-04-08
申请号：US12245686
申请日：2008-10-03
申请人： Stephen Morein , Mark S. Grossman
发明人： Stephen Morein , Mark S. Grossman
IPC分类号： G06F13/36
CPC分类号： G06F13/4027 , G06F13/4031 , G06F13/4068
摘要： An internal bus bridge architecture and method is described. Embodiments include a system with multiple bus endpoints coupled to a bus root via a host bus bridge that is internal to at least one bus endpoint. In addition, the bus endpoints are directly coupled to each other. Embodiments are usable with known bus protocols.
摘要翻译：描述了内部总线桥结构和方法。实施例包括具有通过至少一个总线端点内部的主机总线桥耦合到总线根的多个总线端点的系统。此外，总线端点彼此直接耦合。实施例可用于已知的总线协议。

4. 发明申请

US20090248941A1 Peer-To-Peer Special Purpose Processor Architecture and Method 有权
标题翻译：对等专用处理器架构与方法
公开(公告)号：US20090248941A1
公开(公告)日：2009-10-01
申请号：US12184197
申请日：2008-07-31
申请人： Stephen Morein , Mark S. Grossman , Warren Fritz Kruger , Brian Etscheid
发明人： Stephen Morein , Mark S. Grossman , Warren Fritz Kruger , Brian Etscheid
IPC分类号： G06F13/28 , G06F13/20
CPC分类号： G06F13/4265 , G06F13/4004 , G06F2213/0026
摘要： A peer-to-peer special purpose processor architecture and method is described. Embodiments include a plurality of special purpose processors coupled to a central processing unit via a host bridge bus, a direct bus directly coupling each of the plurality of special purpose processors to at least one other of the plurality of special purpose processors and a memory controller coupled to the plurality of special purpose processors, wherein the at least one memory controller determines whether to transmit data via the host bus or the direct bus, and whether to receive data via the host bus or the direct bus.
摘要翻译：描述了一种对等专用处理器架构和方法。实施例包括经由主桥总线耦合到中央处理单元的多个专用处理器，将多个专用处理器中的每一个直接耦合到多个专用处理器中的至少一个的直接总线和耦合到存储器控制器的存储器控制器至多个专用处理器，其中至少一个存储器控制器确定是经由主机总线还是直接总线发送数据，以及是否经由主机总线或直接总线接收数据。

5. 发明授权

US08892804B2 Internal BUS bridge architecture and method in multi-processor systems 有权
标题翻译：内部BUS桥结构和方法在多处理器系统中
公开(公告)号：US08892804B2
公开(公告)日：2014-11-18
申请号：US12245686
申请日：2008-10-03
申请人： Stephen Morein , Mark S. Grossman
发明人： Stephen Morein , Mark S. Grossman
IPC分类号： G06F13/36 , G06F13/40 , G06F15/16
CPC分类号： G06F13/4027 , G06F13/4031 , G06F13/4068
摘要： An internal bus bridge architecture and method is described. Embodiments include a system with multiple bus endpoints coupled to a bus root via a host bus bridge that is internal to at least one bus endpoint. In addition, the bus endpoints are directly coupled to each other. Embodiments are usable with known bus protocols.
摘要翻译：描述了内部总线桥结构和方法。实施例包括具有通过至少一个总线端点内部的主机总线桥耦合到总线根的多个总线端点的系统。此外，总线端点彼此直接耦合。实施例可用于已知的总线协议。

6. 发明授权

US08161209B2 Peer-to-peer special purpose processor architecture and method 有权
标题翻译：对等专用处理器的架构和方法
公开(公告)号：US08161209B2
公开(公告)日：2012-04-17
申请号：US12184197
申请日：2008-07-31
申请人： Stephen Morein , Mark S. Grossman , Warren Fritz Kruger , Brian Etscheid
发明人： Stephen Morein , Mark S. Grossman , Warren Fritz Kruger , Brian Etscheid
IPC分类号： G06F3/00
CPC分类号： G06F13/4265 , G06F13/4004 , G06F2213/0026
摘要： A peer-to-peer special purpose processor architecture and method is described. Embodiments include a plurality of special purpose processors coupled to a central processing unit via a host bridge bus, a direct bus directly coupling each of the plurality of special purpose processors to at least one other of the plurality of special purpose processors and a memory controller coupled to the plurality of special purpose processors, wherein the at least one memory controller determines whether to transmit data via the host bus or the direct bus, and whether to receive data via the host bus or the direct bus.
摘要翻译：描述了一种对等专用处理器架构和方法。实施例包括经由主桥总线耦合到中央处理单元的多个专用处理器，将多个专用处理器中的每一个直接耦合到多个专用处理器中的至少一个的直接总线和耦合到存储器控制器的存储器控制器至多个专用处理器，其中至少一个存储器控制器确定是经由主机总线还是直接总线发送数据，以及是否经由主机总线或直接总线接收数据。

7. 发明授权

US08587602B2 GPU texture tile detail control 有权
标题翻译： GPU纹理瓷砖细节控制
公开(公告)号：US08587602B2
公开(公告)日：2013-11-19
申请号：US12857280
申请日：2010-08-16
申请人： Mark S. Grossman , Charles N. Boyd , Allison W. Klein , Craig Peeper
发明人： Mark S. Grossman , Charles N. Boyd , Allison W. Klein , Craig Peeper
IPC分类号： G09G5/00
CPC分类号： G06T15/04 , G06T2210/36
摘要： Systems and associated methods for processing textures in a graphical processing unit (GPU) are disclosed. Textures may be managed on a per region (e.g., tile) basis, which allows efficient use of texture memory. Moreover, very large textures may be used. Techniques provide for both texture streaming, as well as sparse textures. A GPU texture unit may be used to intelligently clamp LOD based on a shader specified value. The texture unit may provide feedback to the shader to allow the shader to react conditionally based on whether clamping was used, etc. Per region (e.g., per-tile) independent mipmap stacks may be used to allow very large textures.
摘要翻译：公开了用于在图形处理单元（GPU）中处理纹理的系统和相关方法。可以在每个区域（例如，瓦片）的基础上管理纹理，这允许纹理存储器的有效使用。此外，可以使用非常大的纹理。技术提供纹理流式传输以及稀疏纹理。可以使用GPU纹理单元基于着色器指定值来智能地夹紧LOD。纹理单元可以向着色器提供反馈以允许着色器基于是否使用夹紧等来有条件地进行反应。每个区域（例如，每个图块）独立的mipmap堆栈可以用于允许非常大的纹理。

8. 发明申请

US20120038657A1 GPU TEXTURE TILE DETAIL CONTROL 有权
标题翻译： GPU纹理细节控制
公开(公告)号：US20120038657A1
公开(公告)日：2012-02-16
申请号：US12857280
申请日：2010-08-16
申请人： Mark S. Grossman , Charles N. Boyd , Allison W. Klein , Craig Peeper
发明人： Mark S. Grossman , Charles N. Boyd , Allison W. Klein , Craig Peeper
IPC分类号： G09G5/00
CPC分类号： G06T15/04 , G06T2210/36
摘要： Systems and associated methods for processing textures in a graphical processing unit (GPU) are disclosed. Textures may be managed on a per region (e.g., tile) basis, which allows efficient use of texture memory. Moreover, very large textures may be used. Techniques provide for both texture streaming, as well as sparse textures. A GPU texture unit may be used to intelligently clamp LOD based on a shader specified value. The texture unit may provide feedback to the shader to allow the shader to react conditionally based on whether clamping was used, etc. Per region (e.g., per-tile) independent mipmap stacks may be used to allow very large textures.
摘要翻译：公开了用于在图形处理单元（GPU）中处理纹理的系统和相关方法。可以在每个区域（例如，瓦片）的基础上管理纹理，这允许纹理存储器的有效使用。此外，可以使用非常大的纹理。技术提供纹理流式传输以及稀疏纹理。可以使用GPU纹理单元基于着色器指定值来智能地夹紧LOD。纹理单元可以向着色器提供反馈以允许着色器基于是否使用夹紧等来有条件地进行反应。每个区域（例如，每个图块）独立的mipmap堆栈可以用于允许非常大的纹理。

9. 发明授权

US06532018B1 Combined floating-point logic core and frame buffer 有权
标题翻译：组合浮点逻辑核心和帧缓冲区
公开(公告)号：US06532018B1
公开(公告)日：2003-03-11
申请号：US09294546
申请日：1999-04-19
申请人： Edward C. Chen , Mark S. Grossman , Chi-Shung Wang , John S. Montrym , Mark M. Leather
发明人： Edward C. Chen , Mark S. Grossman , Chi-Shung Wang , John S. Montrym , Mark M. Leather
IPC分类号： G06F1314
CPC分类号： G06T15/005
摘要： A method and apparatus for graphical processing. A logic core to perform pixel fragment manipulation and processing is instantiated on a single substrate with one or more memory units. The memory units are dynamically segmentable into frame buffer and texture memory. Because the logic core is on the same substrate as the memory units, the bandwidth between the core and the memory is greatly increased.
摘要翻译：一种用于图形处理的方法和装置。执行像素片段处理和处理的逻辑核心在具有一个或多个存储器单元的单个衬底上被实例化。存储器单元可动态地分段为帧缓冲器和纹理存储器。由于逻辑核心与存储器单元在同一基板上，因此核心和存储器之间的带宽大大增加。

10. 发明申请

US20090160867A1 Autonomous Context Scheduler For Graphics Processing Units 审中-公开
标题翻译：图形处理单元的自动上下文调度程序
公开(公告)号：US20090160867A1
公开(公告)日：2009-06-25
申请号：US11960305
申请日：2007-12-19
申请人： Mark S. Grossman
发明人： Mark S. Grossman
IPC分类号： G06T1/00
CPC分类号： G06T1/20 , G06T15/005
摘要： Embodiments directed to an autonomous graphics processing unit (GPU) scheduler for a graphics processing system are described. Embodiments include an execution structure for a host CPU and GPU in a computing system that allows the GPU to execute command threads in multiple contexts in a dynamic rather than fixed order based on decisions made by the GPU. This eliminates a significant amount of CPU processing overhead required to schedule GPU command execution order, and allows the GPU to execute commands in an order that is optimized for particular operating conditions. The context list includes parameters that specify task priority and resource requirements for each context. The GPU includes a scheduler component that determines the availability of system resources and directs execution of commands to the appropriate system resources, and in accordance with the priority defined by the context list.
摘要翻译：描述了针对图形处理系统的自主图形处理单元（GPU）调度器的实施例。实施例包括用于计算系统中的主机CPU和GPU的执行结构，其允许GPU基于由GPU做出的决定以动态而不是固定的顺序在多个上下文中执行命令线程。这消除了调度GPU命令执行顺序所需的大量CPU处理开销，并允许GPU以针对特定操作条件进行优化的顺序执行命令。上下文列表包括为每个上下文指定任务优先级和资源需求的参数。 GPU包括调度器组件，其确定系统资源的可用性并且将命令的执行指向适当的系统资源，并且根据由上下文列表定义的优先级。

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