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    • 1. 发明授权
    • Gas-liquid forced turbulence cooling
    • 气液强制湍流冷却
    • US5131233A
    • 1992-07-21
    • US666362
    • 1991-03-08
    • Seymour R. CrayGregory J. Sherwood
    • Seymour R. CrayGregory J. Sherwood
    • G06F1/20H05K7/20
    • H05K7/20763G06F1/20G06F2200/201Y10S165/908Y10S165/911
    • A cooling system employs a cooling liquid and a cooling gas in a combined thermodynamic cycle to overcome the flow resistance of dense assemblies of heat generating components and to improve heat transfer by inducing turbulence, thereby reducing the effects of thermal hysteresis and boundary layer formation. Sensible heat gain to the cooling liquid and gas and latent heat of vaporization of the cooling liquid also occur in channels through and over the components. The flow of cooling gas propels the cooling liquid through the channels. The cooling system is advantageous for cooling electronic components such as integrated circuits which exhibit relatively high degree of energy and physical density, in supercomputers. The cooling system may also be advantageously combined with an immersion cooling system for the power supply components in the computer.
    • 冷却系统采用组合热力学循环中的冷却液体和冷却气体来克服发热部件致密组件的流动阻力,并通过引起湍流来改善热传递,从而减少热滞后和边界层形成的影响。 对于冷却液体和气体的明显的热增益以及冷却液体的蒸发潜热也发生在穿过部件的通道中。 冷却气体的流动推动冷却液通过通道。 在超级计算机中,冷却系统有利于冷却表现出相当高的能量和物理密度的集成电路的电子部件。 冷却系统还可以有利地与用于计算机中的电源组件的浸没冷却系统组合。
    • 8. 发明授权
    • Gallium arsenide depletion made MESFIT logic cell
    • 砷化镓耗尽使得MESFIT逻辑电池
    • US4965863A
    • 1990-10-23
    • US104758
    • 1987-10-02
    • Seymour R. Cray
    • Seymour R. Cray
    • H01L21/8232H01L27/06H03K19/0185H03K19/0952H03K19/0956
    • H01L27/0605H03K19/018535H03K19/0956
    • A gallium arsenide logic design system is described for designing custom or semi-custom LSI integrated circuits using standard cells from a cell library. D-MESFET transistors and Schottky diodes are used for implementing the cell types in gallium arsenide to produce performance levels of less than 150 pico-second per gate propagation delay. Each integrated circuit die is built from a cell library containing three standard cells. The limitation on the number of standard cells used for logic design allows for fast and efficient turnaround time between logic design and fabrication. A minumum number of masks are required for implementing the custom integrated circuit due to the efficient design of the cell types. The placement and interconnect of the cells on the die are also performed in an efficient manner due to the predefined allowable locations for cell placement and the predefined allowable route channels for the interconnect. A clock amplifier cell is described for the cell library which differentially phase corrects a two-phase clock signal to ensure that the two clock lines are perfectly out of phase at all times. The combination of this strictly controlled two-phase clock with the gallium arsenide cell designs allows digital logic implementations at an LSI level to operate at 1-GHz clock frequencies.
    • 描述了砷化镓逻辑设计系统,用于使用来自单元库的标准单元来设计定制或半定制的LSI集成电路。 D-MESFET晶体管和肖特基二极管用于实现砷化镓中的电池类型,以产生每栅极传播延迟小于150皮秒的性能水平。 每个集成电路管芯由包含三个标准单元的单元库构建。 用于逻辑设计的标准单元数量的限制允许在逻辑设计和制造之间快速有效的周转时间。 由于电池类型的有效设计,需要最少数量的掩模来实现定制集成电路。 由于用于单元布置的预定义的可允许位置和用于互连的预定义的可允许路线通道,芯片上的单元的放置和互连也以有效的方式执行。 对于单元库描述时钟放大器单元,其对差分相位校正两相时钟信号,以确保两个时钟线始终完全异相。 这种严格控制的两相时钟与砷化镓电池设计的组合允许LSI级别的数字逻辑实现在1 GHz时钟频率下工作。