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1. 发明授权

US07683594B2 Intelligent dead time control 有权
标题翻译：智能死区时间控制
公开(公告)号：US07683594B2
公开(公告)日：2010-03-23
申请号：US11757181
申请日：2007-06-01
申请人： Seungbeom Kevin Kim , Todd Vacca , Jason Zhang
发明人： Seungbeom Kevin Kim , Todd Vacca , Jason Zhang
IPC分类号： G05F1/40
CPC分类号： H02M7/219 , H02M1/38
摘要： A circuit for reducing switching losses in a synchronous rectifier of a switching stage including a high-side control transistor and a low-side synchronous transistor coupled at a switching node, the switching stage receiving an input voltage and providing a controlled output voltage at an output node. The circuit including a first circuit portion for sensing waveshape edges of a first signal at a gate terminal of the low-side synchronous transistor and a first voltage to determine a delay between the waveshape edge of the first signal and the waveshape edge of the first voltage; and a second circuit portion for calibrating the first signal and the first voltage to align the waveshape edge of the first signal and the waveshape edge of the first voltage, with an optional offset to achieve minimal power loss.
摘要翻译：一种用于降低开关级的同步整流器中的开关损耗的电路，包括耦合在开关节点处的高侧控制晶体管和低侧同步晶体管，所述开关级接收输入电压并在输出端提供受控的输出电压节点。该电路包括用于感测低侧同步晶体管的栅极端处的第一信号的波形边缘的第一电路部分和用于确定第一信号的波形边缘与第一电压的波形边缘之间的延迟的第一电压 ; 以及第二电路部分，用于校准第一信号和第一电压，以使第一信号的波形边缘和第一电压的波形边缘与可选的偏移对准，以实现最小的功率损耗。

2. 发明申请

US20080298101A1 INTELLIGENT DEAD TIME CONTROL 有权
标题翻译：智能死亡时间控制
公开(公告)号：US20080298101A1
公开(公告)日：2008-12-04
申请号：US11757181
申请日：2007-06-01
申请人： Seungbeom Kevin Kim , Todd Vacca , Jason Zhang
发明人： Seungbeom Kevin Kim , Todd Vacca , Jason Zhang
IPC分类号： H02M7/04 , H02M7/217
CPC分类号： H02M7/219 , H02M1/38
摘要： A circuit for reducing switching losses in a synchronous rectifier of a switching stage including a high-side control transistor and a low-side synchronous transistor coupled at a switching node, the switching stage receiving an input voltage and providing a controlled output voltage at an output node. The circuit including a first circuit portion for sensing waveshape edges of a first signal at a gate terminal of the low-side synchronous transistor and a first voltage to determine a delay between the waveshape edge of the first signal and the waveshape edge of the first voltage; and a second circuit portion for calibrating the first signal and the first voltage to align the waveshape edge of the first signal and the waveshape edge of the first voltage, with an optional offset to achieve minimal power loss.
摘要翻译：一种用于降低开关级的同步整流器中的开关损耗的电路，包括耦合在开关节点处的高侧控制晶体管和低侧同步晶体管，所述开关级接收输入电压并在输出端提供受控的输出电压节点。该电路包括用于感测低侧同步晶体管的栅极端处的第一信号的波形边缘的第一电路部分和用于确定第一信号的波形边缘与第一电压的波形边缘之间的延迟的第一电压 ; 以及第二电路部分，用于校准第一信号和第一电压，以使第一信号的波形边缘和第一电压的波形边缘与可选的偏移对准，以实现最小的功率损耗。

3. 发明授权

US08912773B2 Synchronous buck converter including multi-mode control for light load efficiency and related method 有权
标题翻译：同步降压转换器包括多模式控制，轻负载效率及相关方法
公开(公告)号：US08912773B2
公开(公告)日：2014-12-16
申请号：US13111638
申请日：2011-05-19
申请人： Parviz Parto , Seungbeom Kevin Kim , Amir M. Rahimi , Suresh Kariyadan
发明人： Parviz Parto , Seungbeom Kevin Kim , Amir M. Rahimi , Suresh Kariyadan
IPC分类号： G05F1/575 , H02M3/158 , H02M1/00
CPC分类号： H02M3/1588 , H02M2001/0032 , Y02B70/1466 , Y02B70/16
摘要： According to one embodiment, a synchronous buck converter comprises a multi-mode control circuit for detecting a load condition of a variable load, an output stage driven by the multi-mode control circuit, wherein the variable load is coupled to the output stage, and a feedback circuit connected between the output stage and the multi-mode control circuit. The multi-mode control circuit is configured to adjust a current provided by the output stage to the variable load based on the load condition. In one embodiment, the multi-mode control circuit selectably uses one of at least a first control mode and a second control mode according to the load condition, wherein the first control mode is a pulse-width modulation (PWM) mode selected for switching efficiency when the load condition is heavy and the second control mode is an adaptive ON-time (AOT) mode selected for switching efficiency when the load condition is light.
摘要翻译：根据一个实施例，同步降压转换器包括用于检测可变负载的负载状态的多模式控制电路，由多模式控制电路驱动的输出级，其中可变负载耦合到输出级，以及连接在输出级和多模式控制电路之间的反馈电路。多模式控制电路被配置为基于负载条件将由输出级提供的电流调整到可变负载。在一个实施例中，多模式控制电路根据负载条件可选择地使用至少第一控制模式和第二控制模式中的一个，其中第一控制模式是选择用于开关效率的脉冲宽度调制（PWM）模式当负载条件较重时，第二控制模式是当负载条件较轻时选择用于开关效率的自适应导通时间（AOT）模式。

4. 发明申请

US20120187928A1 Synchronous Buck Converter Including Multi-Mode Control for Light Load Efficiency and Related Method 有权
标题翻译：包括多模式控制的同步降压转换器，用于轻载效率和相关方法
公开(公告)号：US20120187928A1
公开(公告)日：2012-07-26
申请号：US13111638
申请日：2011-05-19
申请人： Parviz Parto , Seungbeom Kevin Kim , Amir M. Rahimi , Suresh Kariyadan
发明人： Parviz Parto , Seungbeom Kevin Kim , Amir M. Rahimi , Suresh Kariyadan
IPC分类号： G05F1/46
CPC分类号： H02M3/1588 , H02M2001/0032 , Y02B70/1466 , Y02B70/16
摘要： According to one embodiment, a synchronous buck converter comprises a multi-mode control circuit for detecting a load condition of a variable load, an output stage driven by the multi-mode control circuit, wherein the variable load is coupled to the output stage, and a feedback circuit connected between the output stage and the multi-mode control circuit. The multi-mode control circuit is configured to adjust a current provided by the output stage to the variable load based on the load condition. In one embodiment, the multi-mode control circuit selectably uses one of at least a first control mode and a second control mode according to the load condition, wherein the first control mode is a pulse-width modulation (PWM) mode selected for switching efficiency when the load condition is heavy and the second control mode is an adaptive ON-time (AOT) mode selected for switching efficiency when the load condition is light.
摘要翻译：根据一个实施例，同步降压转换器包括用于检测可变负载的负载状态的多模式控制电路，由多模式控制电路驱动的输出级，其中可变负载耦合到输出级，以及连接在输出级和多模式控制电路之间的反馈电路。多模式控制电路被配置为基于负载条件将由输出级提供的电流调整到可变负载。在一个实施例中，多模式控制电路根据负载条件可选择地使用至少第一控制模式和第二控制模式中的一个，其中第一控制模式是选择用于开关效率的脉冲宽度调制（PWM）模式当负载条件较重时，第二控制模式是当负载条件较轻时选择用于开关效率的自适应导通时间（AOT）模式。

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